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參數(shù)資料
| 型號： | TMP90CM36 |
| 廠商： | Toshiba Corporation |
| 元件分類： | 通用總線功能 |
| 英文描述： | High Speed Advanced CMOS 8-bit Microcontroller,Integrating RAM，ROM，General Serial Interface,Multifuction Timer/Event Counter，Signal Selector Circuit,PWM Output(高速、先進(jìn)的 CMOS 8位微控制器（芯片集成了ROM，RAM，通用串行接口，多功能定時器/事件計數(shù)器,信號選擇電路，PWM輸出）) |
| 中文描述： | 采用先進(jìn)的CMOS高速8位微控制器，集成內(nèi)存，光盤，通用串行接口，Multifuction定時器/事件計數(shù)器，信號選擇器電路，PWM輸出（高速，先進(jìn)的的CMOS 8位微控制器（芯片集成了ROM和RAM內(nèi)存，通用串行接口，多功能定時器/事件計數(shù)器，信號選擇電路，脈寬調(diào)制輸出）） |
| 文件頁數(shù)： | 120/194頁 |
| 文件大?。?/td> | 7013K |
| 代理商： | TMP90CM36 |
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TOSHIBA CORPORATION
TMP90CM36
Receiving control
1) I/O interface mode
When in SCLK1 output mode with the setting of
SCCR1 <IOC1> = “0”, RxD1 signal will be sampled at
the rising edge of shift clock which is output to SLCK
pin.
When in SCLK1 input mode with the setting of SCCR1
<IOC1> = “1”, RxD1 signal will be sampled at the ris-
ing edge or the falling edge of SCLK1 input according
to the setting of SCCR1 <SCLKC1> register.
2) Asynchronous communication (UART) mode
The receiving control has a circuit for detecting the start
bit by the rule of majority. When two or more “0” are
detected during 3 samples, it is recognized as normal
start bit and the reciving operation is started.
Data being received are also evaluated by the rule of
majority.
Receiving buffer
To prevent overrun from occurring, the receiving buffer
has a double structure. Received data are stored one
bit by one bit in the receiving buffer 1 (shift register
type). When 7 bits or 8 bits of data are stored in the
receiving buffer 1, the stored data are transferred to
another receiving buffer 2 (SCBUF1), generating an
interrupt INTRX1. The CPU reads only receiving buffer
2 (SCBUF1). Even before the CPU reads the receiving
buffer 2 (SCBUF1), the received data can be stored in
receiving buffer 1 . However, unless the receiving
buffer 2 (SCBUF1) is read before all bits of the next
data are received by the receiving buffer 1, an overrun
error occurs. If an overrun error occurs, the contents of
receiving buffer 1 will be lost, although the contents of
receiving buffer 2 and SCCR1 <RB81> is still pre-
served.
The parity bit added in 8-bit UART mode and the most
significant bit (MSB) in 9-bit UART mode are stored in
SCCR1 <RB81>.
When in 9-bit UART, the wake-up function of the slave
controllers is enabled by setting SCMOD1 <WU1> to
“1”, and interrupt INTRX occurs only when SCCR1
<RB81> is set to “1”.
Transmission counter
Transmission counter is a 4-bit binary counter which is
used in asynchronous communication (UART) mode
and, like a receiving counter, counts by SIOCLK1
clock, generating TxDCLK1 every 16 clock pulses.
Transmission controller
1) I/O interface mode
In SCLK1 output mode with the setting of SCCR1
<IOC1> = “0”, the data in the transmission buffer are
output bit by bit to TxD1 pin at the rising edge of shift
clock which is output from SLCK1 pin.
In SCLK1 input mode with the setting of SCCR1
<IOC1> = “1”, the data in the transmission buffer are
output bit by bit to TxD1 pin at the rising edge or falling
edge of SCLK input according to the setting of
SCCR1 <SCLKC1> register.
2) Asynchronous communication (UART) mode
When the transmission data are written in the trans-
mission buffer sent from the CPU, transmission starts
at the rising edge of the next TxDCLK1, generating a
transmission shift clock TxDSFT1.
Transmission buffer
Transmission buffer SCBUF1 shifts out and sends the
transmission data written from the CPU from the least
significant bit (LSB) in order, using transmission shift
clock TxDSFT1 which is generated by the transmis-
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| TMP90CM36F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| TMP90CM36T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| TMP90CM37F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| TMP90CM37T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| TMP90CM38F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
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