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參數(shù)資料
| 型號(hào)： | TMP90CM36 |
| 廠商： | Toshiba Corporation |
| 元件分類： | 通用總線功能 |
| 英文描述： | High Speed Advanced CMOS 8-bit Microcontroller,Integrating RAM，ROM，General Serial Interface,Multifuction Timer/Event Counter，Signal Selector Circuit,PWM Output(高速、先進(jìn)的 CMOS 8位微控制器（芯片集成了ROM，RAM，通用串行接口，多功能定時(shí)器/事件計(jì)數(shù)器,信號(hào)選擇電路，PWM輸出）) |
| 中文描述： | 采用先進(jìn)的CMOS高速8位微控制器，集成內(nèi)存，光盤，通用串行接口，Multifuction定時(shí)器/事件計(jì)數(shù)器，信號(hào)選擇器電路，PWM輸出（高速，先進(jìn)的的CMOS 8位微控制器（芯片集成了ROM和RAM內(nèi)存，通用串行接口，多功能定時(shí)器/事件計(jì)數(shù)器，信號(hào)選擇電路，脈寬調(diào)制輸出）） |
| 文件頁數(shù)： | 105/194頁 |
| 文件大小： | 7013K |
| 代理商： | TMP90CM36 |
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TOSHIBA CORPORATION
105
TMP90CM36
Receiving buffer
To prevent overrun from occurring, the receiving buffer
has a double structure. Received data are stored one
bit by one bit in the receiving buffer 1 (shift register
type). When 7 bits or 8 bits of data are stored in the
receiving buffer 1, the stored data are transferred to
another receiving buffer 2 (SCBUF0), generating an
interrupt INTRX0. The CPU reads only receiving buffer
2 (SCBUF0). Even before the CPU reads the receiving
buffer 2 (SCBUF0), the received data can be stored in
receiving buffer 1 . However, unless the receiving buffer
2 (SCBUF0) is read before all bits of the next data are
received by the receiving buffer 1, an overrun error
occurs. If an overrun error occurs, the contents of
receiving buffer 1 will be lost, although the contents of
receiving buffer 2 and SCCR0 <RB80> is still preserved.
The parity bit added in 8-bit UART mode and the most
significant bit (MSB) in 9-bit UART mode are stored in
SCCR0 <RB80>.
When in 9-bit UART, the wake-up function of the slave
controllers is enabled by setting SCMOD0 <WU0> to
“1”, and interrupt INTRX occurs only when SCCR0
<RB80> is set to “1”.
Transmission counter
Transmission counter is a 4-bit binary counter which is
used in asynchronous communication (UART) mode
and, like a receiving counter, counts by SIOCLK0
clock, generating TxDCLK0 every 16 clock pulses.
Transmission controller
Asynchronous communication (UART) mode
When the transmission data are written in the trans-
mission buffer sent from the CPU, transmission starts
at the rising edge of the next TxDCLK0, generating a
transmission shift clock TxDSFT0.
Transmission buffer
Transmission buffer SCBUF0 shifts out and sends the
transmission data written from the CPU from the least
significant bit (LSB) in order, using transmission shift
clock TxDSFT0 which is generated by the transmis-
sion control. When all bits are shifted out, the transmis-
sion buffer becomes empty and generates INTTX0
interrupt.
Parity control circuit
When serial channel control register SCCR0 <PE0> is
set to “1” , it is possible to transmit and receive data
with parity. However, parity can be added only in 7-bit
UART or 8-bit UART mode. With SCCR0 <EVEN0>
register, even (odd) parity can be selected.
For transmission, parity is automatically generated
according to the data written in the transmission buffer
SCBUF, and data are transmitted after being stored in
SCBUF0 <TB70> when in 7-bit UART mode while in
SCMOD0 <TB80> in 8-bit UART mode. <PE0> and
<EVEN0> must be set before transmission data are
written in the transmission buffer.
For receiving, data are shifted in the receiving buffer 1,
and parity is added after the data are transferred in the
receiving buffer 2 (SCBUF0), and then compared with
<RB70> of SCBUF0 when in 7-bit UART mode and
with SCCR0 <RB80> when in 8-bit UART mode. If
they are not equal, a parity error occurs, and SCCR0
<PERR0> flag is set.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMP90CM36F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| TMP90CM36T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| TMP90CM37F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| TMP90CM37T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| TMP90CM38F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
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