參數資料
型號: TMP86PS27FG
廠商: Toshiba Corporation
英文描述: Zener Diode; Application: General; Pd (mW): 500; Vz (V): 6.6 to 6.9; Condition Iz at Vz (mA): 5; C (pF) max: -; Condition VR at C (V):   ESD (kV) min: -; Package: DO-35
中文描述: 8位微控制器
文件頁數: 53/206頁
文件大?。?/td> 1415K
代理商: TMP86PS27FG
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Page 43
TMP86PS27FG
3.7
External Interrupts
The TMP86PS27FG has 7 external interrupt inputs. These inputs are equipped with digital noise reject circuits
(Pulse inputs of less than a certain time are eliminated as noise).
Edge selection is also possible with INT1 to INT3. The
INT0
/P63 pin can be configured as either an external inter-
rupt input pin or an input/output port, and is configured as an input port during reset.
Edge selection, noise reject control and
INT0
/P63 pin function selection are performed by the external interrupt
control register (EINTCR).
Note 1: In NORMAL1/2 or IDLE1/2 mode, if a signal with no noise is input on an external interrupt pin, it takes a maximum of "sig-
nal establishment time + 6/fs[s]" from the input signal's edge to set the interrupt latch.
Note 2: When INT0EN = "0", IL5 is not set even if a falling edge is detected on the
INT0
pin input.
Note 3: When a pin with more than one function is used as an output and a change occurs in data or input/output status, an inter-
rupt request signal is generated in a pseudo manner. In this case, it is necessary to perform appropriate processing such
as disabling the interrupt enable flag.
Source
Pin
Enable Conditions
Release Edge
Digital Noise Reject
INT0
INT0
IMF
EF5
INT0EN=1
Falling edge
Pulses of less than 2/fc [s] are eliminated as
noise. Pulses of 7/fc [s] or more are considered
to be signals. In the SLOW or the SLEEP mode,
pulses of less than 1/fs [s] are eliminated as
noise. Pulses of 3.5/fs [s] or more are consid-
ered to be signals.
INT1
INT1
IMF
EF6 = 1
Falling edge
or
Rising edge
Pulses of less than 15/fc or 63/fc [s] are elimi-
nated as noise. Pulses of 49/fc or 193/fc [s] or
more are considered to be signals. In the SLOW
or the SLEEP mode, pulses of less than 1/fs [s]
are eliminated as noise. Pulses of 3.5/fs [s] or
more are considered to be signals.
INT2
INT2
IMF
EF8 = 1
Falling edge
or
Rising edge
Pulses of less than 7/fc [s] are eliminated as
noise. Pulses of 25/fc [s] or more are considered
to be signals. In the SLOW or the SLEEP mode,
pulses of less than 1/fs [s] are eliminated as
noise. Pulses of 3.5/fs [s] or more are consid-
ered to be signals.
INT3
INT3
IMF
EF16 = 1
Falling edge
or
Rising edge
Pulses of less than 7/fc [s] are eliminated as
noise. Pulses of 25/fc [s] or more are considered
to be signals. In the SLOW or the SLEEP mode,
pulses of less than 1/fs [s] are eliminated as
noise. Pulses of 3.5/fs [s] or more are consid-
ered to be signals.
INT5
INT5
IMF
EF19 = 1
Falling edge
Pulses of less than 2/fc [s] are eliminated as
noise. Pulses of 7/fc [s] or more are considered
to be signals. In the SLOW or the SLEEP mode,
pulses of less than 1/fs [s] are eliminated as
noise. Pulses of 3.5/fs [s] or more are consid-
ered to be signals.
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相關代理商/技術參數
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TMP86PS27FG(JZ) 制造商:Toshiba America Electronic Components 功能描述:N/A - Bulk
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TMP86PS64F 制造商:TOSHIBA 制造商全稱:Toshiba Semiconductor 功能描述:CMOS 8-BIT MICROCONTROLLER
TMP86PS64FG 制造商:TOSHIBA 制造商全稱:Toshiba Semiconductor 功能描述:8 Bit Microcontroller