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| 型號： | TLV320AIC3110IRHBR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 音頻／視頻放大 |
| 英文描述： | AUDIO AMPLIFIER, PQCC32 |
| 封裝： | 5 X 5 MM, GREEN, PLASTIC, QFN-32 |
| 文件頁數(shù)： | 76/126頁 |
| 文件大?。?/td> | 1528K |
| 代理商： | TLV320AIC3110IRHBR |
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1
0
1
HPF
15
1
N
N z
H
(z)
2
D z
-
+
=
-
1
0
1
LPF
15
1
N
N z
H
(z)
2
D z
-
+
=
-
www.ti.com
SLAS647 – DECEMBER 2009
DRC typically works on the filtered version of the input signal. The input signals have no audio information
at dc and extremely low frequencies; however, they can significantly influence the energy estimation
function in the dynamic range compressor (the DRC). Also, most of the information about signal energy is
concentrated in the low-frequency region of the input signal.
To estimate the energy of the input signal, the signal is first fed to the DRC high-pass filter and then to the
DRC low-pass filter. These filters are implemented as first-order IIR filters given by
(6)
(7)
The coefficients for these filters are 16 bits wide in 2s-complement format and are user-programmable
through register write as given in Table 5-33.
Table 5-33. The DRC HPF and LPF Coefficients
Coefficient
Location
HPF N0
C71 page 9 / register 14 and page 9 / register 15
HPF N1
C72 page 9 / register 16 and page 9 / register 17
HPF D1
C73 page 9 / register 18 and page 9 / register 19
LPF N0
C74 page 9 / register 20 and page 9 / register 21
LPF N1
C75 page 9 / register 22 and page 9 / register 23
LPF D1
C76 page 9 / register 24 and page 9 / register 25
The default values of these coefficients implement a high-pass filter with a cutoff at 0.00166 × DAC_fS,
and a low-pass filter with a cutoff at 0.00033 × DAC_fS.
The output of the DRC high-pass filter is fed to the processing block selected for the DAC channel. The
absolute value of the DRC LPF filter is used for energy estimation within the DRC.
The gain in the DAC digital volume control is controlled by page 0 / register 65 and page 0 / register 66.
When the DRC is enabled, the applied gain is a function of the digital volume control register setting and
the output of the DRC.
The DRC parameters are described in sections that follow.
5.5.4.1
DRC Threshold
The DRC threshold represents the level of the DAC playback signal at which the gain compression
becomes active. The output of the digital volume control in the DAC is compared with the set threshold.
The threshold value is programmable by writing to page 0 / register 68, bits D4–D2. The threshold value
can be adjusted between –3 dBFS and –24 dBFS in steps of 3 dB. Keeping the DRC threshold value too
high may not leave enough time for the DRC block to detect peaking signals, and can cause excessive
distortion at the outputs. Keeping the DRC threshold value too low can limit the perceived loudness of the
output signal.
The recommended DRC threshold value is –24 dB.
When the output signal exceeds the set DRC threshold, the interrupt flag bits at page 0 / register 44,
bits D3–D2 are updated. These flag bits are sticky in nature, and are reset only after they are read back
by the user. The non-sticky versions of the interrupt flags are also available at page 0 / register 46, bits
D3–D2.
Copyright 2009, Texas Instruments Incorporated
APPLICATION INFORMATION
53
Product Folder Link(s): TLV320AIC3110
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