參數(shù)資料
型號： TLV320AIC3110IRHBR
廠商： TEXAS INSTRUMENTS INC
元件分類： 音頻／視頻放大
英文描述： AUDIO AMPLIFIER, PQCC32
封裝： 5 X 5 MM, GREEN, PLASTIC, QFN-32
文件頁數(shù)： 68/126頁
文件大小： 1528K
代理商： TLV320AIC3110IRHBR
1
0
1
15
1
N
N z
H(z)
2
D z
-
+
=
-
SLAS647 – DECEMBER 2009
www.ti.com
5.5.1.3
DAC User-Programmable Filters
Depending on the selected processing block, different types and orders of digital filtering are available. Up
to six biquad sections are available for specific processing blocks.
The coefficients of the available filters are arranged as sequentially-indexed coefficients in two banks. If
adaptive filtering is chosen, the coefficient banks can be switched in real time.
When the DAC is running, the user-programmable filter coefficients are locked and cannot be accessed
for either read or write.
However, the TLV320AIC3110 offers an adaptive filter mode as well. Setting page 8 / register 1, bit D2 = 1
turns on double-buffering of the coefficients. In this mode, filter coefficients can be updated through the
host and activated without stopping and restarting the DAC. This enables advanced adaptive filtering
applications.
In the double-buffering scheme, all coefficients are stored in two buffers (buffers A and B). When the DAC
is running and adaptive filtering mode is turned on, setting page 8 / register 1, bit D0 = 1 switches the
coefficient buffers at the next start of a sampling period. This bit is set back to 0 after the switch occurs. At
the same time, page 8 / register 1, bit D1 toggles.
The flag in page 8 / register 1, bit D1 indicates which of the two buffers is actually in use.
Page 8 / register 1, bit D1 = 0: buffer A is in use by the DAC engine; bit D1 = 1: buffer B is in use.
While the device is running, coefficient updates are always made to the buffer not in use by the DAC,
regardless of the buffer to which the coefficients have been written.
Table 5-25. Adaptive-Mode Filter-Coefficient Buffer Switching
DAC Powered Up
Page 8, Reg 1, Bit D1
Coefficient Buffer in Use
I2C Writes to
Updates
No
0
None
Page 8, Reg 2–3, buffer A
No
0
None
Page 12, Reg 2–3, buffer B
Yes
0
Buffer A
Page 8, Reg 2–3, buffer A
Page 12, Reg 2–3, buffer B
Yes
0
Buffer A
Page 12, Reg 2–3, buffer B
Yes
1
Buffer B
Page 8, Reg 2–3, buffer A
Yes
1
Buffer B
Page 12, Reg 2–3, buffer B
Page 8, Reg 2–3, buffer A
The user-programmable coefficients for the DAC Processing Blocks are defined on pages 8 and 9 for
buffer A and pages 12 and 13 for buffer B.
The coefficients of these filters are each 16-bit, 2s-complement format, occupying two consecutive 8-bit
registers in the register space. Specifically, the filter coefficients are in 1.15 (one dot 15) format with a
range from –1.0 (0x8000) to 0.999969482421875 (0x7FFF) as shown in Figure 5-12.
5.5.1.3.1 First-Order IIR Section
The IIR is of first order and its transfer function is given by
(4)
The frequency response for the first-order IIR section with default coefficients is flat.
46
APPLICATION INFORMATION
Copyright 2009, Texas Instruments Incorporated
Product Folder Link(s): TLV320AIC3110
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