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| 型號(hào)： | TLV320AIC3110IRHBR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 音頻／視頻放大 |
| 英文描述： | AUDIO AMPLIFIER, PQCC32 |
| 封裝： | 5 X 5 MM, GREEN, PLASTIC, QFN-32 |
| 文件頁(yè)數(shù)： | 45/126頁(yè) |
| 文件大小： | 1528K |
| 代理商： | TLV320AIC3110IRHBR |
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www.ti.com
SLAS647 – DECEMBER 2009
Because of the oversampling nature of the audio ADC and the integrated digital decimation filtering,
requirements for analog anti-aliasing filtering are very relaxed. The TLV320AIC3110 integrates a
second-order analog anti-aliasing filter with 20-dB attenuation at 1 MHz. This filter, combined with the
digital decimal filter, provides sufficient anti-aliasing filtering without requiring any external components.
The MIC PGA supports analog gain control from from 0 dB to 59.5 dB in steps of 0.5 dB. These gain
levels can be controlled by writing to page 1 / register 47, bits D6–D0. The PGA gain changes are
implemented with internal soft-stepping. This soft-stepping ensures that volume-control changes occur
smoothly with no audible artifacts. On reset, the MIC PGA gain defaults to a mute condition, with soft
stepping enabled. The ADC soft-stepping control can be enabled or disabled by writing to page 0 /
register 81, bits D1–D0. ADC soft-stepping timing is provided by the internal oscillator and internal divider
logic block.
The input feed-forward resistance for the MIC1LP input of the microphone PGA stage has three settings of
10 k
, 20 k, and 40 k, which are controlled by writing to page 1 / register 48, bits D7 and D6. The input
feed-forward resistance value selected affects the gain of the microphone PGA. The ADC PGA gain for
the MIC1LP input depends on the setting of page 1 / register 48 and page 1 / register 49, bits D7–D6. If
D7–D6 are set to 01, then the ADC PGA has 6 dB more gain with respect to the value programmed using
page 1 / register 47. If D7–D6 are set to 10, then the ADC PGA has the same gain as programmed using
page 1 / register 47. If D7–D6 are set to 11, then the ADC PGA has 6 dB less gain with respect to the
value programmed using page 1 / register 47. The same gain scaling is also valid for the MIC1RP and
MIC1LM input, based on the feed-forward resistance selected using page 1 / register 48, bits D5–D2.
The MIC PGA gain can be controlled either by an AGC loop or as a fixed gain. See Figure 1-1 for the
various analog input routings to the MIC PGA that are supported in the single-ended and differential
configurations. The AGC can be enabled by writing to page 0 / register 86, bit D7. If the AGC is not
enabled, then setting a fixed gain is done by writing to page 1 / register 47, bits D6–D0. Because the
TLV320AIC3110 supports soft-stepping gain changes, a read-only flag on page 0 / register 36, bit D7 is
set whenever the gain applied by the PGA equals the desired value set by the gain register. The MIC PGA
can be enabled by writing to page 1 / register 47, bit D7. ADC muting can be done by writing to page 0 /
register 82, bit D7 and page 1 / register 47, bit D7. Disabling the MIC PGA sets the gain to 0 dB. Muting
the ADC causes the digital output to mute so that the output value remains fixed. When soft-stepping is
enabled, the CODEC_CLKIN signal must stay active until after the ADC power-down register is written, in
order to ensure that soft-stepping to mute has had time to complete. When the ADC POWER UP flag is
no longer set, the CODEC_CLKIN signal can be shut down.
5.4.2
Automatic Gain Control (AGC)
The TLV320AIC3110 includes automatic gain control (AGC) for the microphone inputs. AGC can be used
to maintain nominally constant output-signal amplitude when recording speech signals. This circuitry
automatically adjusts the MIC PGA gain as the input signal becomes overly loud or very weak, such as
when a person speaking into a microphone moves closer to or farther from the microphone. The AGC
algorithm has several programmable settings, including target gain, attack and decay time constants,
noise threshold, and maximum PGA applicable, that allow the algorithm to be fine-tuned for any particular
application. The algorithm uses the absolute average of the signal (which is the average of the absolute
value of the signal) as a measure of the nominal amplitude of the output signal. Because the gain can be
changed at the sample interval time, the AGC algorithm operates at the ADC_fS clock rate.
Target level represents the nominal output level at which the AGC attempts to hold the ADC output signal
level. The TLV320AIC3110 allows programming of eight different target levels, which can be programmed
from –5.5 dB to –24 dB relative to a full-scale signal. Because the TLV320AIC3110 reacts to the signal
absolute average and not to peak levels, it is recommended that the target level be set with enough
margin to avoid clipping at the occurrence of loud sounds.
Copyright 2009, Texas Instruments Incorporated
APPLICATION INFORMATION
25
Product Folder Link(s): TLV320AIC3110
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| TLV320AIC3110IRHBT | 功能描述:接口—CODEC Low-Pwr Audio Codec RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TLV320AIC3111 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Low-Power Audio Codec With Embedded miniDSP and Stereo Class-D Speaker Amplifier |
| TLV320AIC3111_101 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Low-Power Audio Codec With Embedded miniDSP and Stereo Class-D Speaker Amplifier |
| TLV320AIC3111EVM-K | 功能描述:音頻 IC 開發(fā)工具 TLV320AIC3111 Eval Mod RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評(píng)估:TAS5614L 工作電源電壓:12 V to 38 V |
| TLV320AIC3111IRHBR | 功能描述:接口—CODEC Low-Pwr Audio CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
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