參數(shù)資料
型號(hào)： TLC8044FN
廠商： TEXAS INSTRUMENTS INC
元件分類： 模擬信號(hào)調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, PQCC68
封裝： PLASTIC, LCC-68
文件頁(yè)數(shù)： 8/32頁(yè)
文件大?。?/td> 477K
代理商： TLC8044FN
TLC8044
12-BIT ANALOG-TO-DIGITAL INTERFACE FOR
CHARGE-COUPLED DEVICE IMAGE SENSORS FOR SCANNERS
SLAS128 – JUNE 1997
16
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
analog-to-digital converter (continued)
The examples in Tables 1 and 2 assume that the ADC reference terminals RT and RB are set to 3.75 V and
1.25 V, respectively. The signals shown in the tables cover the full-scale range of the ADC. In practice, a reduced
range is used to allow some headroom, accomodating a wider range of input offset voltages. The ADC output
code can be inverted under control of the serial interface. When not in use, the ADC can also be put into standby
mode through the serial interface to reduce system power consumption.
sample modes
Two input sampling modes are provided, normal and correlated double sampling (CDS). Sampling mode
selection is made through the serial interface. All video input timing and sampling is performed relative to the
rising edge of the MCLK clock input signal. MCLK is applied to twice the required ADC conversion rate.
Synchronization of sampling and channel multiplexing to the incoming video signals is performed by the VSMP
input synchronization pulse. Table 3 is a summary of the device operating modes.
normal sampling mode
Figure 11(a) and Figure 11(b) show the timing of signals in normal sampling mode for both color and
monochrome operation.
In color operation, all three input channels are sampled at the same instant on the first rising edge of MCLK after
the VSMP pulse. An internal timing circuit then controls the multiplexing of the three channels to the ADC input
in the R,G,B sequence. In this mode, VSMP is applied at the input pixel rate, and ADC conversions are
performed at three times the input pixel rate.
For monochrome (single channel) operation, VSMP is again applied at the input pixel rate, however, for
monochrome, the ADC is supplied with a continuous stream of samples from a single input channel. Input
channel selection in this mode is achieved through the serial interface.
In both color and monochrome operation, a simple external delay circuit can be used to align the video data with
the sampling instant, provided that the CCD clocks are generated from MCLK. Detailed timings for both cases
are shown in Figures 3 and 4.
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