- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄69494 > TLC8044FN (TEXAS INSTRUMENTS INC) SPECIALTY ANALOG CIRCUIT, PQCC68 PDF資料下載
參數(shù)資料
| 型號(hào)： | TLC8044FN |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 11/32頁 |
| 文件大?。?/td> | 477K |
| 代理商： | TLC8044FN |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁當(dāng)前第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁
TLC8044
12-BIT ANALOG-TO-DIGITAL INTERFACE FOR
CHARGE-COUPLED DEVICE IMAGE SENSORS FOR SCANNERS
SLAS128 – JUNE 1997
19
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
correlated double sampling
Correlated double sampling is a circuit technique for reducing any correlated noise between the reset (black)
level and the video level of the CCD array. Referring to the block diagram shown in Figure 13(a), a sample of
the CCD output is taken and held at the reset level and another sample is taken and held at the video level. These
two levels are subtracted essentially nulling any common signal, and thereby minimizing the correlated noise
that exists at both the reset level and the video level. Figure 13(b) shows relative timing.
Subtractor
Video Out
S/H
AMP
S/H
AMP
Reset Out
VIN
(CCD Output)
Reset
S/H
Video
S/H
Vout = Video Out – Reset Out
(a)
(b)
Reset (Black) Level
Video
VIN
(CCD Output)
Reset S/H
Reset Out
Video S/H
Video Out
ADC Clock
+
–
Figure 13. Samplified Correlated Double Sampling
correlated double sampling mode
In CDS mode, two samples are taken per channel within each pixel period. Figure 12 shows the timing diagram
for this mode of operation. The video signal is sampled during the reset phase and during the video information
with timing defined relative to the VSMP input. The difference between these two samples forms the input to
the ADC. The relative timing of the reset and video samples shown in Figure 12 is the default (post-reset)
condition. The timing of the reset sample relative to the video sample can be advanced by one or retarded by
one or two MCLK periods under control of the serial interface. Figure 1 shows a detailed video input timing
diagram with all four CDS timing options.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TLE2425Y | SPECIALTY ANALOG CIRCUIT, UUC3 |
| TLE2426MJG | SPECIALTY ANALOG CIRCUIT, CDIP8 |
| TLE2426Y | SPECIALTY ANALOG CIRCUIT, UUC8 |
| TLE2426YR | SPECIALTY ANALOG CIRCUIT, UUC7 |
| TLE2426CPR | SPECIALTY ANALOG CIRCUIT, PDIP8 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TLC8101IN | 制造商:Texas Instruments 功能描述:8CH SOURCE DRIVER WITH LATCH 制造商:Texas Instruments 功能描述:8CH SOURCE Drvr w/ Latch |
| TLC8101INE4 | 制造商:Texas Instruments 功能描述:8CH SOURCE DRIVER WITH LATCH 制造商:Texas Instruments 功能描述:8CH SOURCE Drvr w/ Latch |
| TLC8101IPW-P | 制造商:Rochester Electronics LLC 功能描述: 制造商:Texas Instruments 功能描述: |
| TLC8116IPW-P | 制造商:Texas Instruments 功能描述: |
| TLC8144-12CPT | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。