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參數(shù)資料
| 型號： | TLC8044FN |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 27/32頁 |
| 文件大?。?/td> | 477K |
| 代理商： | TLC8044FN |
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TLC8044
12-BIT ANALOG-TO-DIGITAL INTERFACE FOR
CHARGE-COUPLED DEVICE IMAGE SENSORS FOR SCANNERS
SLAS128 – JUNE 1997
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
TYPE
I/O
DESCRIPTION
NAME
NO.
TYPE
I/O
DESCRIPTION
AGND
47
Analog
I
Analog ground (0 V)
AVDD
48
Analog
Positive analog supply (5 V)
BINN
45
Analog
I
Negative blue channel input video
BINP
46
Analog
I
Positive blue channel input video
CC1,0
10, 11
Digital
O
Color code outputs. CC0 and CC1 indicate which channel the current output sample was taken
from (R = 00, G = 01, B = 10).
DAC
44
Analog
O
Buffered midpoint of ADC reference string. DAC is used internally to set DAC reference voltages.
DETOP
13
Digital
O
Threshold detector output (active high). DETOP indicates that the current output pixel has
exceeded the internally programmed threshold for that channel.
DGND
14
Digital
I
Digital ground (0 V)
DVDD1,2
60, 1
Digital
I
Positive digital supply (5 V)
GINN
49
Analog
I
Negative green channel input video
GINP
50
Analog
I
Positive green channel input video
MCLK
55
Digital
I
Master clock. MCLK is applied at either six times or twice the input pixel rate for color and
monochrome operation, respectively. MCLK is divided by two internally to define the ADC sample
rate and to provide the clock source for the DSP section.
OE
53
Digital
I
Output 3-state control. Outputs are enabled when OE = 0.
ONE
59
Digital
I
Odd not even. ONE defines the even and odd pixels when the internal pixel offset correction
registers are in use (even = 0, odd = 1).
OP15–OP0
61-68,
2-9
Digital
O
Digital 16-bit output (3-state). In 8-, 10-, and 12-bit output modes, OP15 is used to indicate that
the output pixel is negative; i.e., OP15 can be used as an under range indicator. OP15 is active
high when indicating under range.
ORNG
12
Digital
O
Over range signal (active high). In 8-, 10-, and 12-bit output modes, this signal indicates that the
current output pixel has exceeded the maximum achievable for the output word length in use.
POC11–POC0
27-38
Digital
I
Pixel offset coefficient input. The POC11–POC0 12-bit word is applied at the multiplexed pixel rate
(i.e., three samples per pixel period in color mode) to correct offset errors in a pixel-by-pixel
fashion.
PSC11–PSC0
15-26
Digital
I
Pixel shading coefficient input. The PSC11–PSC0 12-bit quantity is applied at the multiplexed
pixel rate (i.e., three samples per pixel period in color mode) to correct shading effects in a
pixel-by-pixel fashion.
RESET
39
Digital
I
Reset input (active high). RESET forces a reset of all internal registers in the TLC8044.
RINN
51
Analog
I
Negative red channel input video
RINP
52
Analog
I
Positive red channel input video
RU, RT, RB,
RL
42, 40,
41, 43
Analog
I
ADC reference terminals. The voltage applied between RT (full scale) and RB (zero level). define
the ADC reference range. RU and RL, upper and lower resistor terminals, are used to derive
optimum reference voltages from an external 5-V reference.
SCK
57
Digital
I
Serial clock. Serial interface clock signal.
SDI
58
Digital
I
Serial data in. Serial interface input data signal.
SEN
56
Digital
I
Serial enable
VSMP
54
Digital
I
Video sample synchronization pulse. VSMP applied synchronously with MCLK specifies the point
in time that the input is sampled. The timing of internal multiplexing between the R, G, and B
channels is derived from this signal.
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