
TLC8044
12-BIT ANALOG-TO-DIGITAL INTERFACE FOR
CHARGE-COUPLED DEVICE IMAGE SENSORS FOR SCANNERS
SLAS128 – JUNE 1997
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics, VDD = 5 V, AGND = DGND = 0 V, TA = full range (unless otherwise noted)
(continued)
12-bit ADC
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Resolution
12
Bits
Sampling rate
6
MSPS
Full-scale transition error voltage at xINP (see Note 2)
Single-ended mode,
VI(xINN) = 2.5 V,
DAC code = 000H
–100
100
mV
Zero-scale transition error voltage at xINP (see Note 3)
Single-ended mode,
VI(xINN) = 2.5 V,
DAC code = 000H
–100
100
mV
Full-scale transition error voltage, VI(xINP) – VI(xINN) (see Note 2)
Differential mode,
DAC code = 000H
–25
25
mV
Zero-scale transition error voltage, VI(xINP) – VI(xINN) (see Note 3)
Differential mode,
DAC code = 000H
–25
25
mV
Differential nonlinearity (DNL) (see Note 4)
1.5
LSB
Maximum number of missing codes
0
8
CODES
Integral nonlinearity (INL) (see Note 5)
±2
±5
LSB
NOTES:
2. The full-scale transition at xINP is the difference between the signal input voltage that causes the 4094 to 4095 transition and the
measured reference voltage Vref(RT).
3. The zero-scale transition at xINP is the difference between the signal input voltage that causes the 0 to 1 transition and the reference
voltage Vref(RB).
4. Differential nonlinearity (DNL) is the difference between the measured value between any two adjacent codes and the ideal 1 LSB
value.
5. Integral nonlinearity (INL) is the maximum deviation of the output from the ideal straight line between zero and the full-scale value.
switching characteristics
PARAMETER
MIN
TYP
MAX
UNIT
tpd(D)
Propagation delay time, MCLK
↓ to output valid
50
75
ns
ten(PZE)
Enable time, output, OE
↓ to data valid
70
75
ns
tdis(PEZ) Disable time, output, OE↑ to high impedance
70
25
ns