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參數(shù)資料
| 型號： | TLC34076-110 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Color-Palette(110MHz,與TLC34075兼容，另具24位和16位真彩色模式) |
| 中文描述： | 顏色調(diào)色板（110MHz的，與TLC34075兼容，另具24位和16位真彩色模式） |
| 文件頁數(shù)： | 41/56頁 |
| 文件大?。?/td> | 419K |
| 代理商： | TLC34076-110 |
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PARAMETER
UNIT
3-5
3.6 Switching Characteristics
TLC34076-85
TLC34076-85
MIN
TYP
MAX
SCLK frequency (see Note 7)
VCLK frequency
Enable time, RD low to D<0:7> valid
Disable time, RD high to D<0:7> disabled
Valid time, D<0:7> valid after RD high
Propagation delay, SFLAG/NFLAG
↑
to SCLK high (see Note 8)
Delay time, RD low to D<0:7> starting to turn on
Delay time, selected input clock high/low to DOTCLK (internal signal)
high/low
Delay time, DOTCLK high/low to VCLK high/low
Delay time, VCLK high/low to SCLK high/low (see Note 9)
Delay time, DOTCLK high/low to SCLK high/low
Delay time, DOTCLK high to IOR/IOG/IOB active (analog output delay
time) (seeNote10)
Analog output settling time(seeNote 11)
Delay time, DOTCLK high to HSYNCOUT and VSYNCOUT valid
Pulse duration, SCLK high (see Note 8)
Analog output rise time (see Note 12)
Analog output skew
NOTES: 7. SCLK can drive an output capacitive loads up to 60 pF with worst-case transition time between the 10% and
90% levels less than 4 ns (typical 3 ns). SCLK can drive output capacitive loads up to 120 pF, with typical
transition time (10% to 90%) of 4 ns.
8. This parameter applies when the split shift register transfer (SSRT) function is enabled. See Section 2.9.1
for details.
9. VCLK frequency = SCLK frequency.
10. Measured from the 90% point of the rising edge of DOTCLK to 50% of the full-scale transition.
11. Measured from the 50% point of the full-scale transition to the point at which the output has settled, within
±
1 LSB (settling time does not include clock and data feedthrough).
12. Measured between 10% and 90% of the full-scale transition.
85
85
40
17
MHz
MHz
ns
ns
ns
ns
ns
ten1
tdis1
tv1
tPLH1
td1
5
0
5
20
td2
7
ns
td3
td4
td5
6
ns
ns
ns
0
5
8
td6
20
ns
td7
td8
tw6
tr
8
ns
ns
ns
ns
ns
5
15
55
2
0
2
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