參數(shù)資料
型號： TLC34076-110
廠商： Texas Instruments, Inc.
英文描述： Color-Palette(110MHz,與TLC34075兼容，另具24位和16位真彩色模式)
中文描述： 顏色調(diào)色板（110MHz的，與TLC34075兼容，另具24位和16位真彩色模式）
文件頁數(shù)： 17/56頁
文件大小： 419K
代理商： TLC34076-110
2-5
The trailing edge of VCLK is used internally by the TLC34076 to sample and latch the BLANK input. When
BLANK becomes active, SCLK is disabled as soon as possible. For example, if SCLK is high when the
sampled BLANK goes low, SCLK is allowed to complete the clock cycle and return to the low state. SCLK
will then be held low until the sampled BLANK signal goes high. At this time, SCLK will be enabled to clock
the VRAM again. The TLC34076 video blanking circuitry is designed with sufficient pipeline delay to allow
the internal sampled BLANK signal to align with the pipelined RGB data to the Video DACs. The logic
described above works in situations where the SCLK period is shorter than, equal to, or longer than the
VCLK period.
When the VRAM split shift register operation is performed (see Figure 2–3), the SCLK timing is adjusted
to work with the SFLAG input. Basically, the split shift register operation inserts an SCLK during the BLANK
period. This causes the first group of pixel data to appear at the pixel port during BLANK. The first SCLK
after BLANK then latches this data into the TLC34076. Figure 2–3 shows the case when the SSRT (split
shift register transfer) function is enabled. When a rising edge occurs on the SFLAG input, one SCLK with
a minimum of 15-ns pulse duration is generated after the specified delay. Since this is designed to meet
VRAM timing requirements, the SSRT generated SCLK will replace the first SCLK in the regular shift register
transfer case as previously described. Refer to section 2.9 for a detailed explanation of the SSRT function.
The default divide ratio for SCLK is 1:1, as used in Mode 0.
Depending on the frequency relationship between SCLK and VCLK, their phase relationship could be
critical. Please refer to Appendix C for a more detailed discussion.
2.3.2
VCLK
The VCLK frequency can be selected to be 1/1, 1/2, 1/4, 1/8, 1/16, or 1/32 of that of the dot clock, or it can
be held at a high logic level. The default condition is for VCLK to be held at a high logic level. VCLK is not
used in VGA pass-through mode.
VCLK is used by a GSP or custom-designed control logic to generate control signals (BLANK, HSYNC, and
VSYNC). As can be seen from Figures 2–2, 2–3, 2–4, and 2–5, since the control signals are sampled by
VCLK, it is obvious that VCLK has to be enabled.
2nd
Group
SCLK
at Input Pin
PIXEL DATA
Pipeline Delay)
(Internal Signal
BLANK
for Data Latch)
(Internal LOAD
at Input Pin
BLANK
VCLK
Group
1st
Last Group of Pixel Data
of Pixel Data
Latch Last Group
of Pixel Data
Latch First Group
of Pixel Data
Latch Last Group
3rd
Group
4th
Group
6th
Group
NOTE: Either the SSRT function is disabled (general control register bit 2 = 0), or the SFLAG/NFLAG input is held low
if the SSRT function is enabled (general control register bit 2 = 1).
Figure 2–2. SCLK/VCLK Control Timing (SSRT Disabled,
SCLK Frequency = VCLK Frequency)
相關(guān)PDF資料
PDF描述
TLC34076-85 Color-Palette(85MHz,與TLC34075兼容，另具24位和16位真彩色模式)
TLC34076-170 Color-Palette(170MHz,與TLC34075兼容，另具24位和16位真彩色模式)
TLC34076M-135 Color-Palette(135MHz,與TLC34075兼容，另具24位和16位真彩色模式)
TLC4501(中文) Self-Calibrating Dual Operational Amplifier(先進(jìn)LINEPIC，自校準(zhǔn)精密運(yùn)放)
TLC4502(中文) Self-Calibrating Operational Amplifier(先進(jìn)LINEPIC，雙組自校準(zhǔn)精密運(yùn)放)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TLC34076-135FN 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述:
TLC34076-85FN 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述:
TLC34077 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette Data Manual
TLC34077135FN 制造商:TI 功能描述:*
TLC352 制造商:TI 制造商全稱:Texas Instruments 功能描述:LinCMOSE DUAL DIFFERENTIAL COMPARATOR
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