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參數(shù)資料
| 型號(hào)： | TLC34076-110 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Color-Palette(110MHz,與TLC34075兼容，另具24位和16位真彩色模式) |
| 中文描述： | 顏色調(diào)色板（110MHz的，與TLC34075兼容，另具24位和16位真彩色模式） |
| 文件頁數(shù)： | 16/56頁 |
| 文件大小： | 419K |
| 代理商： | TLC34076-110 |
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FUNCTION
SCLK
BITS
2. . . 0
divide DOTCLK by
divide
DOTCLK
by
1
2
4
8
16
32
BITS
5. . .3
000
001
010
011
100
101
VCLK
2-4
Table 2–4. Output Clock Selection Register Format
BITS
3
0
1
0
1
0
1
X
X
X
X
X
X
X
X
5
0
0
0
0
1
1
1
X
X
X
X
X
X
X
4
0
0
1
1
0
0
1
X
X
X
X
X
X
X
2
X
X
X
X
X
X
X
0
0
0
0
1
1
1
1
X
X
X
X
X
X
X
0
0
1
1
0
0
1
0
X
X
X
X
X
X
X
0
1
0
1
0
1
X
VCLK frequency = DOTCLK frequency
VCLK frequency = DOTCLK frequency/2
VCLK frequency = DOTCLK frequency/4
VCLK frequency = DOTCLK frequency/8
VCLK frequency = DOTCLK frequency/16
VCLK frequency = DOTCLK frequency/32
VCLK output held at logic high level (default condition)§
SCLK frequency = DOTCLK frequency
SCLK frequency = DOTCLK frequency/2
SCLK frequency = DOTCLK frequency/4
SCLK frequency = DOTCLK frequency/8
SCLK frequency = DOTCLK frequency/16
SCLK frequency = DOTCLK frequency/32
SCLK output held at logic level low (default condition)§
Register bits 6 and 7 are don’t carebits.
When the clock selection is altered, a minimum 30-ns delay is incurred before the new clocks
are stabilized and running.
§These lines indicate the power-up conditions required to support the VGA pass-through mode.
Table 2–5. VCLK/SCLK Divide Ratio Selection
(Output Clock Selection Register Value in Hex)
000
001
010
011
100
101
1
2
4
8
16
32
00
08
10
18
20
28
01
09
11
19
21
29
02
0A
12
1A
22
2A
03
0B
13
1B
23
2B
04
0C
14
1C
24
2C
05
0D
15
1D
25
2D
Output clock selection register bits
2.3.1
SCLK
Data is latched inside the device on the rising edge of LOAD, which is basically the same as SCLK but not
disabled during BLANK active period. Therefore, SCLK must be set as a function of the pixel bus width and
the number of bit planes. SCLK can be selected as divisions of 1, 2, 4, 8, 16, or 32 of the dot clock. If SCLK
is not used, the output is switched off and held low to protect against VRAM lock-up due to invalid SCLK
frequencies. SCLK is also held low during the BLANK active period. The SCLK control timing has been
designed to interface directly with the external system VRAM. The shift register in the system VRAM should
be updated during the BLANK-active period. This allows the first SCLK out of BLANK to clock the VRAM
and enable the first group of pixel data to appear on the pixel bus, as well as at the TLC34076 pixel input
port. The second SCLK after BLANK latches the first group of pixel port data into the TLC34076 (see
Figure 2–2).
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相關(guān)代理商/技術(shù)參數(shù) |
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| TLC34076-135FN | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| TLC34076-85FN | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| TLC34077 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette Data Manual |
| TLC34077135FN | 制造商:TI 功能描述:* |
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