參數(shù)資料
型號(hào): TLC34076-110
廠商: Texas Instruments, Inc.
英文描述: Color-Palette(110MHz,與TLC34075兼容,另具24位和16位真彩色模式)
中文描述: 顏色調(diào)色板(110MHz的,與TLC34075兼容,另具24位和16位真彩色模式)
文件頁(yè)數(shù): 32/56頁(yè)
文件大?。?/td> 419K
代理商: TLC34076-110
FUNCTION
2-20
Table 2–10. General Control Register Bit Functions
GENERAL CONTROL REGISTER BIT
6
5
4
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
1
X
0
X
X
1
X
0
X
X
1
X
X
X
X
X
X
X
X
7
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
3
X
X
X
X
X
0
0
1
X
X
X
X
X
X
X
X
2
X
X
X
X
0
1
X
0
X
X
X
X
X
X
X
X
1
X
X
0
1
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
HSYNCOUT is active-low
HSYNCOUT is active-high (default)
VSYNCOUT is active-low
VSYNCOUT is active-high (default)
Disable split shift register transfer (default)
Enable split shift register transfer
Disable special nibble mode (default)
Enable special nibble mode
0-IRE pedestal (default)
7.5-IRE pedestal
Disable sync (default)
Enable sync
Little Endian mode (default)
Big Endian mode
MUXOUT is low (default)
MUXOUT is high
2.11.1
HSYNCOUT and VSYNCOUT polarity inversion is provided to allow indication to monitors of the current
screen resolution. Since the polarities for VGA pass-through mode are provided at the feature connector,
the inputs to the TLC34076 will have the right polarities for monitors already, so the TLC34076 just passes
them through with pipeline delay (see Section 2.8). These two bits only work in the normal modes, and the
input horizontal and vertical syncs are assumed to be active-low incoming pulses. These two bits default
to the value 1 but can be changed by software.
2.11.2
Split Shift Register Transfer Enable (SSRT) and Special Nibble Mode Enable
(SNM) (Bits 2 and 3)
See Section 2.9.
2.11.3
Pedestal Enable Control (Bit 4)
This bit specifies whether a 0- or 7.5-IRE blanking pedestal is to be generated on the video outputs. Having
a 0-IRE blanking pedestal means that the black and blank levels are the same.
0: 0-IRE pedestal (default)
1: 7.5-IRE pedestal
2.11.4
Sync Enable Control (Bit 5)
This bit specifies whether or not SYNC information is to be output onto IOG.
0: Disable sync (default)
1: Enable sync
2.11.5
Little/Big Endian Mode Control (Bit 6)
This bit specifies either Little or Big Endian data format for the pixel bus Frame Buffer Interface (see 2.6.1).
0: Little Endian (default)
1: Big Endian
2.11.6
MUXOUT (Bit 7)
The MUXOUT bit indicates to external circuitry that the device is running in VGA pass-through mode. This
bit does not affect the operation of the device (see Section 2.10).
HSYNCOUT and VSYNCOUT (Bits 0 and 1)
相關(guān)PDF資料
PDF描述
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