參數(shù)資料
型號： TLC320AD50IDWR
廠商： TEXAS INSTRUMENTS INC
元件分類： 模擬信號調理
英文描述： SPECIALTY ANALOG CIRCUIT, PDSO28
封裝： PLASTIC, SO-28
文件頁數(shù)： 42/55頁
文件大小： 506K
代理商： TLC320AD50IDWR
6–2
6.2
Control Register 2
Table 6–3. Control Register 2
D7
D6
D5
D4
D3
D2
D1
D0
DESCRIPTION
X
–
FLAG output value
–
1
–
Phone mode enable
–
0
–
Phone mode disable
–
X
–
Decimator FIR overflow flag (valid only during read cycle)
–
1
–
16-bit ADC mode
–
0
–
Not-16-bit ADC mode [(15+1)– bit mode]
–
X
0
Reserved (TLC320AD50C only)
–
0
FSD enable (TLC320AD52C only)
–
1
–
FSD disable (TLC320AD52C only)
–
1
–
Analog loopback enabled
–
0
–
Analog loopback disabled
Default value: 00000000
Writing 0s to the reserved bits is suggested.
6.3
Control Register 3
The following command contains the frame-sync delay (FSD) register address and loads D7 (MSB)–D0 into the FSD
register. The data byte (D5–D0) determines the number of SCLKs between FS and the delayed frame-sync signal,
FSD. The minimum data value for this portion of the register, bits D5–D0, is decimal 18.
Table 6–4. Control Register 3
D7
D6
D5
D4
D3
D2
D1
D0
DESCRIPTION
–
X
Number of SCLKs between FS and FSD
X
–
Binary number of slave devices (3 maximum for TLC320AC50C, 1 maximum for
TLC320AC52C)
Default value: 00000000
Writing 0s to the reserved bits is suggested.
6.4
Control Register 4
Table 6–5. Control Register 4
D7
D6
D5
D4
D3
D2
D1
D0
DESCRIPTION
–
1
–
Analog input gain = mute
–
1
0
–
Analog input gain = 12 dB
–
0
1
–
Analog input gain = 6 dB
–
0
–
Analog input gain = 0 dB
–
1
Analog output gain = mute
–
1
0
Analog output gain = – 12 dB
–
0
1
Analog output gain = – 6 dB
–
0
Analog output gain = 0 dB
–
X
–
Sample frequency select (N): fs = MCLK/(128 N) or MCLK/(512 N)
1
–
Bypass internal DPLL
0
–
Enable internal DPLL
Default value: 00000000
The value of the sample frequency divisor, N, is determined by the octal representation of bits D4–D6. Hence,
001 = 1, 010 = 2, etc. By setting D4–D6 to 000, N = 8 is selected.
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