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參數(shù)資料
| 型號： | TLC320AD50IDWR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PDSO28 |
| 封裝： | PLASTIC, SO-28 |
| 文件頁數(shù)： | 4/55頁 |
| 文件大?。?/td> | 506K |
| 代理商： | TLC320AD50IDWR |
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1–5
1.5
Terminal Functions (Continued)
TERMINAL
NAME
NO.
PT
NO.
DW
I/O
DESCRIPTION
M/S
29
22
I
Master/slave select input. When M/S is high, the device is the master. When M/S is low, the device is a slave.
MCLK
25
18
I
Master clock. MCLK derives the internal clocks of the sigma-delta analog interface circuit.
MONOUT
40
27
O
Monitor output. MONOUT allows for monitoring of the analog input and is a high-impedance output. The gain
or mute is selected using control 1 register.
OUTM
36
24
O
Inverting output of the DAC. The OUTM output can be loaded with 600
. OUTM is functionally identical with
and complementary to OUTP. OUTM can also be used alone for single-ended operation.
OUTP
35
23
O
Noninverting output of the DAC. The OUTP output can be loaded with 600
. OUTP can also be used alone
for single-ended operation.
PWRDWN
22
16
I
Power down. When PWRDWN is pulled low, the device goes into a power-down mode, the serial interface
is disabled. However, all the register values are sustained and the device resumes full power operation without
reinitialization when PWRDWN is pulled high again. PWRDWN resets the counters only and preserves the
programmed register contents (see paragraph 2.2.2 for more information).
REFM
46
2
O
Voltage reference filter output. REFM is provided for low-pass filtering of the internal bandgap reference. The
optimal ceramic capacitor value is 0.1
F and should be connected between REFM and REFP. DC voltage
at REFM is 0 V.
REFP
45
1
O
Voltage reference filter positive output. REFP is provided for low-pass filtering of the internal bandgap
reference. The optimal ceramic capacitor value is 0.1
F and should be connected between REFP and REFM.
DC voltage at REFP is 3.2 V.
RESET
21
15
I
Reset. RESET initializes all of the internal registers to their default values. The serial port can be configured
to the default state accordingly. See section 6 and paragraph 2.2.1 for more information.
SCLK
26
19
I/O
Shift clock. The SCLK signal clocks serial data in through DIN and out through DOUT during the frame-sync
interval. When configured as an output (M/S high), SCLK is generated internally by multiplying the frame-sync
signal frequency by 256. When configured as an input (M/S low), SCLK is generated externally and must be
synchronous with the master clock and frame sync.
NOTES:
1. Separate analog and digital power and ground pins are supplied on this device. For best operation and results, the PC board designer
should utilize separate analog and digital power supplies as well as separate analog and digital ground planes.
2. All digital inputs and outputs are TTL compatible, unless otherwise noted (for DVDD = 5 V).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TLC320AD50IPT | 制造商:TI 制造商全稱:Texas Instruments 功能描述:SIGMA-DELTA ANALOG INTERFACE CIRCUITS WITH MASTER-SLAVE FUNCTION |
| TLC320AD52CDW | 制造商:TI 制造商全稱:Texas Instruments 功能描述:SIGMA-DELTA ANALOG INTERFACE CIRCUITS WITH MASTER-SLAVE FUNCTION |
| TLC320AD52CPT | 功能描述:IC ANALOG INTERFACE W/MS 48-LQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:PCM 數(shù)據(jù)接口:PCM 音頻接口 分辨率（位）:15 b ADC / DAC 數(shù)量:1 / 1 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):- 動態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):- 電壓 - 電源，模擬:2.7 V ~ 3.3 V 電壓 - 電源，數(shù)字:2.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:80-VFBGA 供應(yīng)商設(shè)備封裝:80-BGA MICROSTAR JUNIOR（5x5） 包裝:帶卷 (TR) 其它名稱:296-21257-2 |
| TLC320AD535 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DUAL CHANNEL VOICE/DATA CODEC |
| TLC320AD535C | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DUAL CHANNEL VOICE/DATA CODEC |
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