參數(shù)資料
型號： TL16PC564BLVPZ
廠商： Texas Instruments, Inc.
英文描述： Tools, Stencil; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):Yes
中文描述： 的PCMCIA通用異步收發(fā)器
文件頁數(shù)： 20/33頁
文件大?。?/td> 488K
代理商： TL16PC564BLVPZ
TL16PC564B, TL16PC564BLV
PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
SLLS225A – MARCH 1996 – REVISED FEBRUARY 1998
20
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
ARBCLK switching characteristics over recommended operating free-air temperature range (see
Figure 14)
TEST CONDITIONS
VCC = 3.3 V,
VCC = 5 V
VCC = 3.3 V,
VCC = 5 V
VCC = 3.3 V,
VCC = 5 V
VCC = 3.3 V,
VCC = 5 V
VCC = 3.3 V,
VCC = 5 V
VCC = 3.3 V,
VCC = 5 V
VCC = 3.3 V,
VCC = 5 V
VCC = 3.3 V,
VCC = 5 V
VCC = 3.3 V,
VCC = 5 V
VCC = 3.3 V,
VCC = 5 V
MIN
26
MAX
UNIT
t4
tc4
Cycle time internal arbitration clock ( ARBCLKI
÷
Cycle time, internal arbitration clock ( ARBCLKI
ARBPGM)
See Note 11
Note 14
ns
14
Note 14
t5
tc5
Cycle time arbitration clock
Cycle time, arbitration clock
See Note 11
26
ns
14
td42
Delay time ARBCLKI
Delay time, ARBCLKI
↑
to ARBCLK0
↑
(
÷
1)
See Note 11
13
ns
7.3
td43
Delay time ARBCLKI
Delay time, ARBCLKI
↓
to ARBCLK0
↓
(
÷
1)
See Note 11
15.5
ns
10
td44
Delay time ARBCLKI
Delay time, ARBCLKI
↑
to ARBCLK0
↑
(
÷
2)
See Note 11
15.3
ns
8.8
td45
Delay time ARBCLKI
Delay time, ARBCLKI
↑
to ARBCLK0
↓
(
÷
2)
See Note 11
17.5
ns
11
td46
Delay time ARBCLKI
Delay time, ARBCLKI
↑
to ARBCLK0
↑
(
÷
4)
See Note 11
19.5
ns
11.5
td47
Delay time ARBCLKI
Delay time, ARBCLKI
↑
to ARBCLK0
↓
(
÷
4)
See Note 11
21.5
ns
13.5
td48
Delay time ARBCLKI
Delay time, ARBCLKI
↑
to ARBCLK0
↑
(
÷
8)
See Note 11
22.7
ns
13.5
25
td49
Delay time ARBCLKI
Delay time, ARBCLKI
↑
to ARBCLK0
↓
(
÷
8)
See Note 11
ns
15.7
NOTES: 11. TL16PC564BLV device tested at 3 V.
14. tc4 MAX = N/6, where N = shortest (in ns) of the two attribute-memory accesses, host CPU or subsystem.
reset timing requirements over recommended ranges of operating free-air temperature and supply
voltage (unless otherwise noted) (see Figure 15)
TEST CONDITIONS
MIN
8
tc5
8
tc5
MAX
UNIT
tw22
tw23
Pulse duration, RESET active
ns
Pulse duration, RESET inactive
ns
td50
Delay time ARBCLKI
Delay time, ARBCLKI
↑
to RST low
VCC = 3.3 V,
VCC = 5 V
VCC = 3.3 V,
VCC = 5 V
See Note 11
10.4
ns
7.5
13.9
td51
Delay time ARBCLKI
Delay time, ARBCLKI
↑
to RST high impedance
See Note 11
ns
9.7
NOTE 11: TL16PC564BLV device tested at 3 V.
subsystem interrupt-request timing requirements over recommended ranges of operating free-air
temperature and supply voltage (see Figure 16)
MIN
MAX
UNIT
td52
Delay time, WE
↑
to IRQ
↑
(see Note 15)
2tc5
3tc5
ARBCLKI
cycles
td53
Delay time, SCR bit 6
↑
to IRQ
↓
(see Note 16)
tc5
2tc5
ARBCLKI
cycles
NOTES: 11. TL16PC564BLV device tested at 3 V.
15. Synchronized to rising edge of ARBCLKI
16. Synchronized to falling edge of ARBCLKI
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TL16PIR552PH 功能描述:UART 接口集成電路 Dual UART w/Dl IrDA & 1284 Parallel Port RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
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