參數(shù)資料
型號： TL16PC564BLVPZ
廠商： Texas Instruments, Inc.
英文描述： Tools, Stencil; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):Yes
中文描述： 的PCMCIA通用異步收發(fā)器
文件頁數(shù)： 15/33頁
文件大小： 488K
代理商： TL16PC564BLVPZ
TL16PC564B, TL16PC564BLV
PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
SLLS225A – MARCH 1996 – REVISED FEBRUARY 1998
15
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
XIN timing requirements over recommended operating free-air temperature range (see Figure 1)
TEST CONDITIONS
VCC = 3.3 V,
VCC = 5 V
VCC = 3.3 V,
VCC = 5 V
VCC = 3.3 V,
VCC = 5 V
VCC = 3.3 V,
VCC = 5 V
MIN
MAX
UNIT
Input frequency
See Note 11
50
MHz
60
t1
tc1
Cycle time XIN
Cycle time, XIN
See Note 11
20
ns
16.7
t1
tw1
Pulse duration XIN clock high
Pulse duration, XIN clock high
See Note 11
10
ns
8
t2
tw2
Pulse duration XIN clock low
Pulse duration, XIN clock low
See Note 11
10
ns
8
NOTE 11: TL16PC564BLV device tested at VCC = 3 V.
clock switching characteristics over recommended operating free-air temperature range (see
Figure 1)
PARAMETER
TEST CONDITIONS
VCC = 3.3 V,
VCC = 5 V
VCC = 3.3 V,
VCC = 5 V
VCC = 3.3 V,
VCC = 5 V
VCC = 3.3 V,
VCC = 5 V
VCC = 3.3 V,
VCC = 5 V
MIN
MAX
UNIT
td1
Delay time XIN
Delay time, XIN
↑
to UARTCLK
↑
See Note 11
14
ns
8
td2
Delay time XIN
Delay time, XIN
↓
to UARTCLK
↓
See Note 11
16
10
ns
td3
Delay time XIN
Delay time, XIN
↑
to UARTCLK
↓
See Note 11
19.8
13
ns
td4
Delay time XIN
Delay time, XIN
↑
to UARTCLK
↑
See Note 11
20.6
13.5
ns
td5
Delay time XIN
Delay time, XIN
↓
to UARTCLK
↑
See Note 11
21
ns
13.8
NOTE 11: TL16PC564BLV device tested at VCC = 3 V.
host CPU I/O read-cycle timing requirements over recommended ranges of operating free-air
temperature and supply voltage (see Figure 2 and Note 12)
MIN
MAX
UNIT
th1
th2
tw4
tsu1
tsu2
th3
th4
tsu3
td6
NOTE 12: The maximum load on INPACK is one low power shot with 50-pF total load. All timing is measured in nanoseconds.
Hold time, HA(9–0) valid after IORD
↑
Hold time, REG
↑
valid after IORD
↑
Pulse duration, IORD low
Setup time, HA(9–0) valid before IORD
↓
Setup time, CEx
↓
before IORD
↓
Hold time, CEx
↑
after IORD
↑
Hold time, HD(7–0) valid after IORD
↑
Setup time, REG
↓
before IORD
↓
Delay time, HD(7–0) valid after IORD
↓
20
ns
0
ns
165
ns
70
ns
5
ns
20
ns
0
ns
5
ns
100
ns
host CPU I/O read-cycle switching characteristics over recommended ranges of operating free-air
temperature and supply voltage (see Figure 2 and Note 11)
PARAMETER
MIN
MAX
UNIT
td7
td8
NOTE 12: The maximum load on INPACK is one low power Schottky (LSTTL) diode with 50-pF total load. All timing is measured in nanoseconds.
Delay time, INPACK
↓
after IORD
↓
Delay time, INPACK
↑
after IORD
↑
45
ns
45
ns
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