參數(shù)資料
型號： TL16PC564BLVPZ
廠商： Texas Instruments, Inc.
英文描述： Tools, Stencil; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):Yes
中文描述： 的PCMCIA通用異步收發(fā)器
文件頁數(shù)： 10/33頁
文件大?。?/td> 488K
代理商： TL16PC564BLVPZ
TL16PC564B, TL16PC564BLV
PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
SLLS225A – MARCH 1996 – REVISED FEBRUARY 1998
10
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
host CPU/UART interface
The UART select is derived from either host CPU address information or logic levels on CE1, CE2 and REG.
In the address mode, host CPU address bits HA9, HA7, HA6, HA5, and HA3 are combined with conditional
derivatives of HA4 and HA8 to select the UART (HA4 and HA8 select COM ports 1–4 based on settings in the
subsystem control register). CE1 and CE2 are combined such that either of these two signals in combination
with REG enable the UART in the event that these signals are present. In the event that CE1 or CE2 are not
present, the UART must be accessed in the address mode previously described. The UART select in
conjunction with IORD and IOWR allows host CPU accesses to the UART. Host CPU address bits HA2–HA0
are decoded to select which UART register is to be accessed.
All UART registers remain intact with the exception of the FIFO control register (FCR) and the modem-control
register (MCR). The FCR (host CPU write-only address 2) bits 4 and 5 in conjunction with EXTEND control RTS
operation and FIFO depth as follows:
BIT 5
BIT 4
EXTEND
RTS OPERATION
FIFO DEPTH
X
X
H
Normal
16 bytes
0
0
L
Normal
16 bytes
0
1
L
Auto
16 bytes
1
0
L
Normal
64 bytes
1
1
L
Auto
64 bytes
FCR bit 5 high and EXTEND low redefine the receiver FIFO trigger levels set by FCR bits 6 and 7 as follows:
BIT 7
BIT 6
TRIGGER LEVEL
0
0
1
0
1
16
1
0
32
1
1
56
The MCR (host CPU address 4) bit 5 is read only. Bit 5 is controlled by the subsystem to enable (high) the
auto-CTS mode of operation
subsystem/UART interface
The UART provides a serial-communications channel to the subsystem with enhanced RTS control (see
auto-RTS description). This channel is capable of operating at 115 kbps and is the main communications
channel to the subsystem (refer to the TL16C550 specification for the detailed description of the
serial-communications channel).
Many of the UART registers have been mapped into the subsystems memory space as read only. In addition,
MCR bit 5 (subsystem address 130 hex) is controlled by the subsystem to enable (high) auto-CTS. The
subsystem can read the MCR at address 134 hex. When reading the FCR (subsystem address 132 hex), bits
1 and 2 are always high, and bits 4 and 5 are low only when EXTEND is low and the host CPU has set them
high (64-byte FIFOs and auto-RTS enabled) (refer to the subsystem memory map).
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TL16PC564BPZ 功能描述:UART 接口集成電路 Sngl UART w/64-Byte FIFOs PCMCIA Ifc RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
TL16PC564BPZG4 功能描述:UART 接口集成電路 Sgl UART w/64-Byte Fifos RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
TL16PIR552 制造商:TI 制造商全稱:Texas Instruments 功能描述:DUAL UART WITH DUAL IrDA AND 1284 PARALLEL PORT
TL16PIR552PH 功能描述:UART 接口集成電路 Dual UART w/Dl IrDA & 1284 Parallel Port RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
TL16PIR552PHG4 功能描述:UART 接口集成電路 DUAL UART W/DUAL IRDA & 1284 PORT RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
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