參數(shù)資料
型號(hào)： THMC50SSOPDBQ
廠商： Texas Instruments, Inc.
英文描述： KPT 55C 55#20 SKT RECP
中文描述： 遠(yuǎn)程/本地溫度監(jiān)視器和通風(fēng)機(jī)的SMBus接口控制器
文件頁(yè)數(shù)： 24/32頁(yè)
文件大?。?/td> 437K
代理商： THMC50SSOPDBQ
THMC50
REMOTE/LOCAL TEMPERATURE MONITOR AND
FAN CONTROLLER WITH SMBus INTERFACE
SLIS090 – JULY 1999
24
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
NAND tree tests - FAN_SPD/NTEST_IN and ADD/NTEST_OUT (continued)
NOTE:
To properly implement the NAND tree test on the PCB, no terminals listed in the tree should be
connected directly to power or ground. If it is necessary to permanently connect a terminal to
ground, such as an address terminal, it should be connected to ground through a low value resistor,
such as 3.3 k
, to allow the system-level ATE to drive it high. All terminals listed in the NAND tree
which need to be permanently tied high should be pulled up to the supply via a resistor to allow the
ATE to drive the node low during the NAND tree test.
registers and RAM
REGISTERS AND RAM
A7 - A0 IN HEX
POWER ON VALUE OF REGISTERS: <7:0> IN BINARY
Configuration register
0x40
0010 0101
Interrupt status register
0x41
0000 0000
Interrupt mask register
0x43
0000 0000
Interrupt status register mirror
0x4C
0000 0000
Value RAM
0x13 – 0x3D, 0x43 – 0x4A
See value RAM section for complete description
Company ID
0x3E
Contains company number
Stepping
0x3F
Contains stepping number and device version
register 0x40 configuration register
BIT
NAME
R/W
DESCRIPTION
0
Start
Read/write
Setting this bit to a 1 enables start-up of the THMC50; clearing this bit to 0 places the THMC50 in
standby mode.
Caution: The INT output is not cleared if this bit was cleared after an interrupt has occurred (see INT
clear bit).
At start-up, temperature monitoring and limit checking functions begin. Note: All limit values should
be programmed into the THMC50 prior to using the standard thermal interrupt mechanism based
upon high and low limits. (power-up default=1)
1
INT enable
Read/write
Setting this bit to a 1 enables the INT output. 1=enabled 0=disabled (power-up default = 0)
2
INT clear
Read/Write
This bit clears the INT output when set (1) without affecting the contents of the interrupt status
register. (power-up default = 1)
3
Programmable
automatic trip
point control
register write
once bit
Read/write
once
Setting this bit to a 1 locks in the values set into the programmable remote thermal diode automatic
trip point and programmable ambient temperature automatic trip point (value RAM locations 0x14
and 0x13). Furthermore when this bit is set, the values in the default remote thermal diode
automatic trip point and default ambient temperature automatic trip point (value RAM locations
0x18 and 0x17) no longer have an effect on the THERM, FAN_SPD, or FAN_OFF outputs. This
register is unable to be written again until AUXRST is asserted. (power-up default = 0)
4
Soft reset
Read/write
Setting this bit to a 1 restores power-up default values to the configuration register, interrupt status
register, interrupt status register mirror, and interrupt mask register. This bit automatically clears
itself since the power-on default is zero.
5
FAN_OFF
Read/write
Setting this bit to a 1 causes the FAN_OFF terminal to be floated. Clearing this bit to 0 causes the
FAN_OFF terminal to be driven low which requests that the fan be turned off. This bit is
unconditionally set if the THERM terminal is ever asserted. Reading this bit reflects the state of the
FAN_OFF output buffer. Due to the open drain nature of this terminal, the value read does not
represent the actual state of the external net connected to it. (power-up default =1)
6
GPI invert
Read/write
Setting this bit to a 1 inverts the GPI input for the purpose of level detection and interrupt generation.
Clearing this bit to 0 leaves the GPI input unmodified. (power-up default=0)
7
Reserved
Read/write
Reserved (default = 0)
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