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參數(shù)資料
| 型號(hào)： | THMC50SSOPDBQ |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | KPT 55C 55#20 SKT RECP |
| 中文描述： | 遠(yuǎn)程/本地溫度監(jiān)視器和通風(fēng)機(jī)的SMBus接口控制器 |
| 文件頁數(shù)： | 22/32頁 |
| 文件大小： | 437K |
| 代理商： | THMC50SSOPDBQ |
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THMC50
REMOTE/LOCAL TEMPERATURE MONITOR AND
FAN CONTROLLER WITH SMBus INTERFACE
SLIS090 – JULY 1999
22
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
interrupt clearing (continued)
The INT output can be cleared with the INT clear bit (bit 2 of the configuration register) without affecting the
contents of the interrupt status register.
reset generators
The THMC50 contains the equivalent of two MAX811 microprocessor voltage monitors for generation of system
resets. One of these functions monitors the THMC50 VCC3 terminal connected to the system’s 3.3-V main
power supply. The other function monitors the VCC3AUX terminal connected to the system’s 3.3-V auxiliary
power supply. Each function has a corresponding reset output (RST, AUXRST) that is used by the core logic
for proper system hardware initialization.
When a particular power supply voltage falls below a threshold of 2.93V (max), the associated reset output is
asserted low for at least 140 ms after the power supply voltage has risen above the threshold (see Figure 18
and Figure 20). The reset outputs are a logic 0 for V
CC
(VCC3 or VCC3AUX) > 1 V.
The THMC50 includes a manual reset input, MR. When asserted low (0), the RST output is asserted low. This
output remains asserted as long as the MR input is asserted. Once MR is negated, this reset output continues
to be asserted for 180 ms (typical) (see Figure 17). The MR input may be used by test equipment or external
logic (e.g., front bezel panel reset button) to initiate a reset independent of power supply voltage status. It is
recommended that a 0.1-
μ
F capacitor be connected between MR and ground if the terminal is connected to a
long lead/cable length.
Asserting the AUXRST output causes the RST output to also be asserted regardless of the voltage level on the
VCC3 terminal. This insures that the auxiliary reset output (AUXRST) is negated before the RST output is
negated. Once AUXRST is negated, the RST output continues to remain asserted for 180 ms (typical) (see
Figure 19).
The AUXRST terminal is bidirectional. It can be driven by an external device to force the THMC50 into a hard
reset condition. Insure that other devices connected to AUXRST are not also reset, if that is an undesirable
behavior. If AUXRST is only used as an output, then isolation is not necessary.
reset generators timing diagrams
Figure 17 through Figure 20 illustrate the timing relationship of the THMC50 reset generators.
Figure 17 shows RST output behavior when the MR input is asserted low.
Figure 18 shows RST output behavior according to the voltage seen at the VCC3 terminal.
Figure 19 shows RST output behavior whenever an AUXRST is generated or is asserted manually.
Figure 20 shows AUXRST output and RST output behavior according to the voltage seen at the VCC3AUX
terminal.
Figure 17. MR to RST Timing
Figure 18. VCC3 to RST Timing
MR
RST
TIME
t(RP)
t(MR)
VCC3
RST
2.93V
TIME
t(RP)
t(VCC3RST)
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