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參數(shù)資料
| 型號： | THMC50SSOPDBQ |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | KPT 55C 55#20 SKT RECP |
| 中文描述： | 遠程/本地溫度監(jiān)視器和通風(fēng)機的SMBus接口控制器 |
| 文件頁數(shù)： | 23/32頁 |
| 文件大?。?/td> | 437K |
| 代理商： | THMC50SSOPDBQ |
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THMC50
REMOTE/LOCAL TEMPERATURE MONITOR AND
FAN CONTROLLER WITH SMBus INTERFACE
SLIS090 – JULY 1999
23
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
reset generators timing diagrams (continued)
Figure 19. AUXRST to RST Timing
Figure 20. VCC3AUX, AUXRST, and RST Timing
RST
TIME
AUXRST
t(RP)
t(RST)
VCC3AUX
AUXRST
2.93V
TIME
RST
t(RP)
t(RP)
t(VCC3AUX1)
t(VCC3AUX2)
NAND tree tests - FAN_SPD/NTEST_IN and ADD/NTEST_OUT
A NAND tree is provided in the THMC50 for automated test equipment (ATE) board level connectivity testing.
If a logic 1 is applied to the FAN_SPD/NTEST_IN input terminal during initial power up, the device is in the NAND
tree test mode and the ADD/NTEST_OUT terminal becomes the NAND tree output. Power must be removed
from the device in order to return to normal operation. To perform a NAND tree test, MR, SDA, SCL, and GPI
terminals should be initially driven low, and FAN_SPD/NTEST_IN initially driven high. Starting with MR and
ending with GPI, each input should be toggled high and left high. This results in ADD/NTEST_OUT reflecting
the following pattern: (1 –> 0 –> 1 –> 0 –> 1) (see Figure 21).
Allow for a typical propagation delay of 500 ns.
GPI
SCL
SDA
MR
ADD/NTEST_OUT
D
Q
AUXRST
FAN_SPD/NTEST_IN
ENABLE
ENABLE
GPI
SCL
SDA
MR
ADD/NTEST_OUT
0
0
0
0
1
0
0
0
1
0
0
0
1
1
1
0
1
1
1
0
1
1
1
1
1
Figure 21. NAND Tree Test Equivalent Circuit
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