參數(shù)資料
型號： TDA9105A
廠商： 意法半導(dǎo)體
英文描述： DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
中文描述： 偏轉(zhuǎn)處理器多同步監(jiān)測儀
文件頁數(shù)： 7/31頁
文件大?。?/td> 340K
代理商： TDA9105A
VERTICALSECTION
OperatingConditions
Symbol
VSVR
VEWM
VDHPCM
VDHPCm
VDFm
Rload
Parameter
Min.
0
Typ.
Max.
5.5
6.5
6.5
Unit
V
V
V
V
V
M
Vertical Sync Input Voltage (Pin 34)
Maximum EW Output Voltage (Pin 37)
Maximum Dynamic Horizontal Phase Control Output Voltage (Pin 40)
Minimum Dynamic Horizontal Phase Control Output Voltage (Pin 40)
Minimum Vertical Dynamic Focus Output Voltage (Pin 1)
Minimum Load for lessthan 1% Vertical Amplitude Drift (Pin 25)
0.9
0.9
65
9
ElectricalCharacteristics
(V
CC
= 12V,T
amb
= 25
°
C)
Symbol
I
BIASP
I
BIASN
VSth
Parameter
TestConditions
For V
28
= 2V
For V
31
= 6V,V
29
= 6V
High-level
Low-level
V
34
= 0.8V
Min.
Typ.
2
0.5
Max.
Unit
μ
A
μ
A
V
V
μ
A
BiasCurrent(currentsourcedbyPNPBase)(Pin28)
Bias Current(Pins 29-31) (sinked by NPNbase)
Vertical Sync Input ThresholdVoltage (Pin 34)
2
0.8
VSBI
Vertical Sync Input Bias Current
(Current Sourced by PNP Base)
Voltage at Ramp Bottom Point (Pin 27)
Voltageat Ramp TopPoint(with Sync) (Pin27)
Voltage at Ramp Top Point (without Sync)
(Pin 27)
Minimum Vertical Sync Pulse Width (Pin 34)
Vertical Sync Input Maximum Duty-cycle
(Pin 34)
Vertical Sawtooth Discharge Time Duration
(Pin 27)
Vertical Free Running Frequency
1
V
RB
V
RT
V
RTF
2/8
5/8
V
REF-V
V
REF-V
V
V
RT
-0.1
VSW
VSmDut
5
μ
S
%
15
VSTD
With 150nF cap
70
μ
S
VFRF
V
= 2V, V
grounded,
Measured onPin 27
Cosc (Pin27) = 150nF
With C
27
= 150nF
V
= 6V, C
= 150nF
50Hz < f < 185Hz
V
28
, V
29
grounded
V
33
= 2V
V
33
= 4V
V
33
= 6V
100
Hz
ASFR
RAFD
AUTO-SYNC Frequency (see Note 1)
Ramp Amplitude Drift Versus Frequency
50
185
Hz
100
ppm/Hz
Rlin
Vpos
Ramp Linearityon Pin 30
Vertical Position Adjustment Voltage (Pin 32)
0.5
3.2
3.5
3.8
±
2
%
V
V
V
mA
3.65
3.3
I
VPOS
Max Currenton VerticalPosition Control Output
(Pin 32)
Vertical Output Voltage (Pin 30)
(peak-to-peak voltage on Pin30)
V
OR
V
31
= 2V
V
31
= 4V
V
31
= 6V
See Note 2
3.75
2
3
4
2.2
V
V
V
V
OUTDC
V0I
dVS
DC Voltage on Vertical Output (Pin30)
Vertical Output Maximum Current (Pin 30)
Max Vertical S-Correction Amplitude
V
28
= 2V inhibits S-CORR
V
28
= 6V gives maximum S-CORR
Max Vertical C-Correction Amplitude
7/16
±
5
V
REF-V
mA
V/V
30pp
at T/4
V/V
30pp
at 3T/4
V
29
= 2V
V
29
= 4V
V
29
= 6V
TBD
-4
+4
-1.6
0
1.6
1
TBD
%
%
%
%
%
V
V
μ
A
Ccorr
TBD
TBD
VFly Th
VFly Inh
I
BIAS DCIN
Notes :
1. It is the frequency range for which the VERTICAL OSCILLATORwill automaticallysynchronize, using a single capacitorvalue on
Pin 27 and with a constant ramp amplitude.
2. Typically 3.5Vfor Vertical reference voltage typical value (8V).
Vertical Flyback Threshold (Pin 36)
Inhibition of Vertical Flyback Input (Pin 36)
Bias Current (Pin 35) (sourced by PNP base)
TBD
See Note 1
For V
35
= V
32
V
REF
- 0.5
2
9
TDA9105A
7/31
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