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參數(shù)資料
| 型號： | TDA9105A |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | DEFLECTION PROCESSOR FOR MULTISYNC MONITORS |
| 中文描述： | 偏轉(zhuǎn)處理器多同步監(jiān)測儀 |
| 文件頁數(shù)： | 16/31頁 |
| 文件大?。?/td> | 340K |
| 代理商： | TDA9105A |
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OPERATING DESCRIPTION
(continued)
The PLL1 ensures the coincidence between the
leading edge of the synchro signal and a phase
reference obtained by comparison between the
sawtooth of the VCO and an internal DC voltage
adjustablebetween 2.4V and 4V (by Pin15). So a
±
45
°
phaseadjustmentis possible(seeFigure11).
20k
220nF
13
From
Phase
Comparator
NOR1
A
6.5V
B
H-Lock CAP
2
HLOCKOUT
9
Figure 15 :
LOCK/UNLOCKBlock Diagram
H Osc
Sawtooth
Phase REF1
H Synchro
1.6V
Vb
6.4V
2.4V<Vb<4V
0.75T
0.25T
Phase REF1is obtainedbycomparisonbetweenthesawtoothand
a DC voltage adjustablebetween 2.4Vand 4V. The PLL1ensures
the exact
coincidence between the signals phase REF and
HSYNS. A
±
T/8 phase adjustment is possible.
9
Figure 14 :
PLL1 TimingDiagram
Thetwo VCOthresholdcan befilteredby connect-
ing capacitoron Pins 8-9.
The TDA9103 also includes a LOCK/UNLOCK
identification block which senses in real-time
whetherthePLLis lockedon theincominghorizon-
tal sync signal or not. The resulting information is
availableon HLOCKOUToutput (Pin2). The block
diagram of the LOCK/UNLOCK function is de-
scribed in Figure12.
TheNOR1 gate is receivingthephase comparator
outputpulses (which also drive the charge pump).
Whenthe PLLis locked,on point
A
there is a very
small negative pulse (100ns) at each horizontal
cycle, so after R-C filter, there is a high level on
Pin13 whichforce HLOCKOUT to high level(pro-
vided that HLOCKOUT is pulledup to V
CC
).
When the PLL is unlocked, the 100ns negative
pulseon
A
becomesmuchlargerandconsequently
the average level on Pin 13 will decrease. When it
reaches 6.5V, point
B
goes to low level forcing
HLOCKOUT output to “0”.
Thestatusof Pin13 isapproximatelythefollowing:
- Near 0V when there is no H-SYNC,
- Between0and4Vwith H-SYNCfrequencydiffer-
ent from VCO,
- Between4 and 8V when H-SYNCfrequency
= VCOfrequencybut not in phase,
- Near to 8V when PLL is locked.
It is importantto noticethat Pin 13 is not an output
pinandmustonlybeusedforfilteringpurpose(see
Figure12).
TDA9105A
16/31
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