參數(shù)資料
型號： TDA9105A
廠商： 意法半導(dǎo)體
英文描述： DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
中文描述： 偏轉(zhuǎn)處理器多同步監(jiān)測儀
文件頁數(shù)： 6/31頁
文件大小： 340K
代理商： TDA9105A
HORIZONTAL SECTION
(continued)
ElectricalCharacteristics
(V
CC
= 12V,T
amb
= 25
°
C)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
SUPPLY AND REFERENCE VOLTAGES
V
CC
I
CC
V
REF-H
I
REF-H
V
REF-V
I
REF-V
Supply Voltage (Pin 18)
Supply Current (Pin 18)
Reference Voltage for Horizontal Section (Pin 7)
Max Sourced Current onV
REF-H
(Pin 7)
Reference Voltage for Vertical Section (Pin 26)
Max Sourced Current onV
REF-V
(Pin 26)
10.8
12
45
8
13.2
65
8.6
5
8.6
5
V
See Figure 1
I = 2mA
mA
V
mA
V
mA
7.4
I = 2mA
7.4
8
INPUT SECTION/PLL1
V
INTH
Horizontal Input Threshold Voltage (Pin 17)
Low level voltage
High level voltage
V
REF-H
= 8V
R0 = 6.49k
, C0 = 680pF
% of Horizontal period
2
0.8
V
V
VCO
V
COG
Hph
f0
CR
VCO Control Voltage (Pin 12)
VCO Gain, dF/dV (Pin12)
Horizontal Phase Adjust (Pin 15)
FreeRunning Frequency(adjustable bychanging R0) R0 = 6.49k
, C0 = 680pF
PLL1 Capture Range
1.6 to 6.2
17
±
12.5
27
V
kHz/V
%
kHz
25
29
Fh Min
Fh Max
PLL ON
PLL OFF
R0 = 6.49k
, C0 = 680pF
See conditions on Fig. 1
f0
3.7 x f0
kHz
kHz
V
V
mA
V
PLLinh
PLL 1 Inhibition (Pin 14)
(Typ. Threshold = 1.6V)
Max Output Current on HLock Output
Low Level Voltage on HLock Output
V
14
V
14
I
2
V
2
with I
2
= 10mA
2
0.8
I
HLock0
V
HLock0
10
0.5
0.25
SECOND PLL AND HORIZONTALOUTPUT SECTION
FBth
Hjit
Flyback Input Threshold Voltage (Pin 5)
Horizontal Jitter
See Figure 14
See Application Diagram
(Pins 8-9)
0.60
0.70
80
V
ppm
HDmin
HDmax
HDvd
Horizontal Drive Output Duty-cycle
(Pin 20 or 21) (see Note)
Minimum
Maximum
Horizontal Drive Low Level Output Voltage
V
4
= 2V
V
4
= 6V
V
4
= V
REF
- 500mV
Pin 20 to GND,
V
21
-V
20
, I
OUT
= 20mA
Pin 21 to V
CC
,
I
OUT
= 20mA
31
54.5
33.2
57
61.5
1.1
35.5
59.5
%
%
%
V
1.7
HDem
Horizontal Drive High Level Output Voltage
(output on Pin20)
X-RAY Protection Input Threshold Voltage (Pin16)
Maximum OutputCurrent on Composite Blanking
Output
Low-Level Voltageon CompositeBlankingOutput
(Blanking ON)
Internal Clamping Voltage on 2nd PLLLoop Filter
Output (Pin 3)
Threshold Voltage to Stop H-out, V-out and to
activate BLKout (OFF mode when V
4
< V
OFF
)
(Pin 4)
Supply Voltage to Stop H-out, V-out when
V
CC
< VSCinh (Pin18)
9.5
10
V
XRAYth
ISblkO
TBD
8
TBD
10
V
I
22
mA
VSblkO
V
22
with I
22
= 10mA
0.25
0.5
V
Vphi2
Vmin
Vmax
V
4
1.6
4.0
V
V
V
V
OFF
1
VSCinh
TBD
7.5
V
Note :
If H-drive is taken on Pin 20 (Pin 21 connected to supply), H-D is the ratio of low level durationto horizontal period.
If H-drive is taken on Pin 21 (Pin 20 grounded), H-D is the ratio of high level duration to horizontal period.
Inboth cases, H-D period driving horizontalscanning transistor off.
9
TDA9105A
6/31
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