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參數(shù)資料
| 型號： | TDA9105A |
| 廠商： | 意法半導體 |
| 英文描述： | DEFLECTION PROCESSOR FOR MULTISYNC MONITORS |
| 中文描述： | 偏轉(zhuǎn)處理器多同步監(jiān)測儀 |
| 文件頁數(shù)： | 17/31頁 |
| 文件大小： | 340K |
| 代理商： | TDA9105A |
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H Osc
Sawtooth
H Drive
1.6V
4V
6.4V
0.75T
0.25T
Ts
Duty Cycle
Internally
Shaped Flyback
Flyback
9
The duty cycle of H-drive is adjustable between 30% and 50%.
Figure 16 :
PLL2 TimingDiagram
20k
Q1
GND 0V
5
HFLY
400
9
Figure 17 :
Flyback Input Electrical Diagram
OPERATING DESCRIPTION
(continued)
PLL2
The PLL2 ensures a constant position of the
shapedflybacksignal in comparisonwith the saw-
tooth of the VCO(see Figure 13).
The phase comparator of PLL2 is followed by a
charge pump with a
±
0.5mA(typ.) output current.
TheflybackinputiscomposedofanNPNtransistor.
This input has to be current driven.
The maximum recommandedinput current is 2mA
(seeFigures 14 and 15).
C Lockdet
LOCKDET
COMP1
INPUT
INTERFACE
CHARGE
PUMP
PLL
INHIBITION
Horizontal
Adjust
15
VCO
PHASE
ADJUST
PLL1INHIB
R0 C0
11 10
Filter
12
High
Low
E2
3.2V
OSC
COMP2
CHARGE
PUMP
High
Low
RAP
CYC
EN
Adjust
Rapcyc
4
Cap
PHi2
3
PWM
LOGI
PWM
BUFFER
FLYBACK
SortCOLL
Flyback
SortEM
VB
VA
Horizontal
Input
13
14
17
5
21
20
HLOCKOUT
2
4V
9
Figure 18 :
Dual PLLBlock Diagram
TDA9105A
17/31
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