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參數(shù)資料
| 型號(hào)： | TDA8357J |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 偏轉(zhuǎn) |
| 英文描述： | Full bridge current driven vertical deflection output circuit in LVDMOS(LVDMOS中的整橋電流驅(qū)動(dòng)的垂直偏轉(zhuǎn)輸出電路) |
| 中文描述： | VERTICAL DEFLECTION IC, PZIP9 |
| 封裝： | POWER, PLASTIC, SOT-523-1, DIL-BENT-SIL, 9 PIN |
| 文件頁數(shù)： | 7/16頁 |
| 文件大小： | 96K |
| 代理商： | TDA8357J |
1999 Nov 10
7
Philips Semiconductors
Preliminary specification
Full bridge vertical deflection output circuit
in LVDMOS
TDA8357J
Notes
1.
To limit V
OUTA
to 68 V, V
FB
must be 66 V due to the voltage drop of the internal flyback diode between pins OUTA
and V
FB
at the first part of the flyback.
Allowable input range: V
I(bias)
+ V
i(dif)
< 1600 mV and V
I(bias)
V
i(dif)
> 100 mV for each input.
This value specifies the sum of the voltage losses of the internal current paths between pins V
P
and OUTA, and
between pins OUTB and GND. Specified for T
j
= 125
°
C. The temperature coefficient for V
loss(1)
is a positive value.
This value specifies the sum of the voltage losses of the internal current paths between pins V
P
and OUTB, and
between pins OUTA and GND. Specified for T
j
= 125
°
C. The temperature coefficient for V
loss(2)
is a positive value.
The linearity error is measured for a linear input signal without S-correction and is based on the ‘on screen’
measurement principle. This method is defined as follows. The output signal is divided in 22 successive equal time
blocks k. The 1st and 22nd blocks are ignored, while the voltage amplitudes are measured across R
M
, starting at
k = 2 and ending at k = 21, where V
k
and V
k+1
are the measured voltages of two successive blocks. V
min
, V
max
and
V
avg
are the minimum, maximum and average voltages respectively. The linearity errors are defined as:
2.
3.
4.
5.
a)
(adjacent blocks)
b)
(non adjacent blocks)
6.
The linearity errors are specified for a minimum input voltage of 300 mV (p-p). Lower input voltages lead to voltage
dependent S-distortion in the input stage.
7.
8.
Pin FEEDB not connected.
9.
10. V
P(ripple)
= 500 mV (RMS value); 50 Hz < f
P(ripple)
< 1 kHz; measured across R
M
.
11. This value specifies the internal voltage loss of the current path between pins V
FB
and OUTA.
Flyback switch
I
o(peak)
V
loss(FB)
maximum (peak) output current
voltage loss at flyback
t
≤
1.5 ms
note 11
I
o
= 0.7 A
I
o
= 1.0 A
±
1.2
A
7.5
8
8.5
9
V
V
Guard circuit
V
O(grd)
V
O(grd)(max)
guard output voltage
allowable guard voltage
I
O(grd)
= 100
μ
A
maximum leakage current
I
L(max)
= 10
μ
A
V
O(grd)
= 0 V; not active
V
O(grd)
= 4.5 V; active
5
6
7
18
V
V
I
O(grd)
output current
1
10
2.5
μ
A
mA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
LE
V
-------V
V
1
+
–
avg
=
LE
V
-------------------------------
V
–
V
avg
=
G
v ol
)
V
V
FEEDB
OUTB
V
OUTB
–
------------------------V
=
G
v
V
INA
V
OUTB
V
INB
–
–
-------V
=
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| TDA8358 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full bridge vertical deflection output circuit in LVDMOS with east-west amplifier |
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