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參數(shù)資料
| 型號： | TDA8024 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | ECONOLINE: RB & RA - Dual Output from a Single Input Rail- Power Sharing on Output- Industry Standard Pinout- 1kVDC & 2kVDC Isolation- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 85% |
| 中文描述： | IC卡接口 |
| 文件頁數(shù)： | 11/29頁 |
| 文件大小： | 172K |
| 代理商： | TDA8024 |
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2004 July 12
11
Philips Semiconductors
Product specification
IC card interface
TDA8024
8.5
Inactive mode
After a Power-on reset, the circuit enters the inactive
mode. A minimum number of circuits are active while
waiting for the microcontroller to start a session:
All card contacts are inactive (approximately 200
to
GND)
Pins I/OUC, AUX1UC and AUX2UC are in the
high-impedance state (11 k
pull-up resistor to V
DD
)
Voltage generators are stopped
XTAL oscillator is running
Voltage supervisor is active
The internal oscillator is running at its low frequency.
8.6
Activation sequence
After power-on and after the internal pulse width delay, the
system microcontroller can check the presence of a card
using the signals OFF and CMDVCC as shown in Table 2.
Table 2
Card presence indication
If the card is in the reader (this is the case if PRES or
PRES is active), the system microcontroller can start a
card session by pulling CMDVCC LOW. The following
sequence then occurs (see Fig.6):
1.
CMDVCC is pulled LOW and the internal oscillator
changes to its high frequency (t
0
).
The voltage doubler is started (between t
0
and t
1
).
V
CC
rises from 0 to 5 V (or 3 V) with a controlled slope
(t
2
= t
1
+ 1.5
×
T) where T is 64 times the period of the
internal oscillator (approximately 25
μ
s).
I/O, AUX1 and AUX2 are enabled (t
3
= t
1
+ 4T) (these
were pulled LOW until this moment).
CLK is applied to the C3 contact of the card reader (t
4
).
RST is enabled (t
5
= t
1
+ 7T).
2.
3.
4.
5.
6.
The clock may be applied to the card using the following
sequence:
1.
Set RSTIN HIGH.
2.
Set CMDVCC LOW.
3.
Reset RSTIN LOW between t
3
and t
5
; CLK will start at
this moment.
4.
RST remains LOW until t
5
, when RST is enabled to be
the copy of RSTIN.
5.
After t
5
, RSTIN has no further affect on CLK; this
allows a precise count of CLK pulses before toggling
RST.
If the applied clock is not needed, then CMDVCC may be
set LOW with RSTIN LOW. In this case, CLK will start at t
3
(minimum 200 ns after the transition on I/O), and after t
5
,
RSTIN may be set HIGH in order to obtain an Answer To
Request (ATR) from the card.
Activation should not be performed with RSTIN held
permanently HIGH.
0
(2)
(1)
6
4
2
0
20
40
t (ns)
Vo
(V)
12
8
4
0
Io
(mA)
60
FCE661
Fig.6
I/O, AUX1 and AUX2 output voltage and
current as functions of time during a
LOW-to-HIGH transition.
(1) Current.
(2) Voltage.
OFF
CMDVCC
INDICATION
HIGH
LOW
HIGH
HIGH
card present
card not present
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| TDA8024AT | 制造商:NXP Semiconductors 功能描述: 制造商:PHILIPS-SEMI 功能描述: |
| TDA8024AT/C1,112 | 功能描述:輸入/輸出控制器接口集成電路 IOCTRL 5V 1.5A 0.56W RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
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| TDA8024T | 制造商:NXP Semiconductors 功能描述: |
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