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參數(shù)資料
| 型號： | TDA8024 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | ECONOLINE: RB & RA - Dual Output from a Single Input Rail- Power Sharing on Output- Industry Standard Pinout- 1kVDC & 2kVDC Isolation- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 85% |
| 中文描述： | IC卡接口 |
| 文件頁數(shù)： | 10/29頁 |
| 文件大小： | 172K |
| 代理商： | TDA8024 |
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2004 July 12
10
Philips Semiconductors
Product specification
IC card interface
TDA8024
8.3
Clock circuitry
The card clock signal (CLK) is derived from a clock signal
input to pin XTAL1 or from a crystal operating at up to
26 MHz connected between pins XTAL1 and XTAL2.
The clock frequency can be f
XTAL
,
1
/
2
×
f
XTAL
,
1
/
4
×
f
XTAL
or
1
/
8
×
f
XTAL
. Frequency selection is made via
inputs CLKDIV1 and CLKDIV2 (see Table 1).
Table 1
Clock frequency selection; note 1
Note
1.
Thestatusofpins CLKDIV1andCLKDIV2mustnotbe
changed simultaneously; a delay of 10 ns minimum
between changes is needed; the minimum duration of
any state of CLK is eight periods of XTAL1.
The frequency change is synchronous, which means that
during transition no pulse is shorter than 45% of the
smallest period, and that the first and last clock pulses
about the instant of change have the correct width.
When changing the frequency dynamically, the change is
effective for only eight periods of XTAL1 after the
command.
The duty factor of f
XTAL
depends on the signal present at
pin XTAL1.
In order to reach a 45 to 55% duty factor on pin CLK, the
input signal on pin XTAL1 should have a duty factor of
48 to 52% and transition times of less than 5% of the input
signal period.
If a crystal is used, the duty factor on pin CLK may be
45 to 55% depending on the circuit layout and on the
crystal characteristics and frequency.
In other cases, the duty factor on pin CLK is guaranteed
between 45 and 55% of the clock period.
ThecrystaloscillatorrunsassoonastheICispoweredup.
If the crystal oscillator is used, or if the clock pulse on
pin XTAL1 is permanent, the clock pulse is applied to the
cardasshownin theactivationsequencesshown inFigs 7
and 8.
If the signal applied to XTAL1 is controlled by the system
microcontroller, the clock pulse will be applied to the card
when it is sent by the system microcontroller (after
completion of the activation sequence).
8.4
I/O transceivers
The three data lines I/O, AUX1 and AUX2 are identical.
The idle state is realized by both I/O and I/OUC lines being
pulled HIGH via a 11 k
resistor (I/O to V
CC
and I/OUC to
V
DD
).
Pin I/O is referenced to V
CC
, and pin I/OUC to V
DD
, thus
allowing operation when V
CC
is not equal to V
DD
.
The first side of the transceiver to receive a falling edge
becomes the master. An anti-latch circuit disables the
detection of falling edges on the line of the other side,
which then becomes a slave.
After a time delay t
d(edge)
, an N transistor on the slave side
is turned on, thus transmitting the logic 0 present on the
master side.
When the master side returns to logic 1, a P transistor on
the slave side is turned on during the time delay t
pu
and
then both sides return to their idle states.
This active pull-up feature ensures fast LOW-to-HIGH
transitions;asshowninFig.6,itisabletodelivermorethan
1 mA at an output voltage of up to 0.9V
CC
into an 80 pF
load. At the end of the active pull-up pulse, the output
voltage depends only on the internal pull-up resistor and
the load current.
The current to and from the card I/O lines is limited
internally to 15 mA and the maximum frequency on these
lines is 1 MHz.
CLKDIV1
CLKDIV2
f
CLK
0
0
0
1
1
1
1
0
f
XTAL
f
8
------------
f
4
------------
f
2
------------
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TDA8024AT | 制造商:NXP Semiconductors 功能描述: 制造商:PHILIPS-SEMI 功能描述: |
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| TDA8024AT/C1,118 | 功能描述:功率放大器 IC Card Interface 28-Pin RoHS:否 制造商:TriQuint Semiconductor 封裝 / 箱體: 工作電源電壓:28 V 電源電流:2.5 A 工作溫度范圍: 封裝: |
| TDA8024T | 制造商:NXP Semiconductors 功能描述: |
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