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參數(shù)資料
| 型號： | TDA7514 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | SINGLE-CHIP FM/AM TUNER WITH STEREO DECODER AND AUDIO PROCESSOR |
| 中文描述： | 單芯片F(xiàn)M /調(diào)幅調(diào)諧立體聲解碼器和音頻處理器 |
| 文件頁數(shù)： | 26/74頁 |
| 文件大?。?/td> | 604K |
| 代理商： | TDA7514 |
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TDA7514
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The TDA7514 supports the I
2
C-Bus protocol. This protocol defines any device that sends data onto the
bus as a transmitter, and the receiving device as the receiver. The device that controls the transfer is a
master and device being controlled is the slave. The master will always initiate data transfer and provide
the clock to transmit or receive operations. The TDA7514 is always a slave.
I
2
C-BUS INTERFACE
4.1 Data Transition
Data transition on the SDA line must only occur when the clock SCL is LOW. SDA transitions while SCL
is HIGH will be interpreted as START or STOP condition.
4.2 Start Condition
A start condition is defined by a HIGH to LOW transition of the SDA line while SCL is at a stable HIGH
level. This "START" condition must precede any command and initiate a data transfer onto the bus. The
device continuously monitors the SDA and SCL lines for a valid START and will not response to any com-
mand if this condition has not been met.
4.3 Stop Condition
A STOP condition is defined by a LOW to HIGH transition of the SDA while the SCL line is at a stable
HIGH level. This condition terminates the communication between the devices and forces the bus inter-
face of the device into the initial condition.
4.4 Acknowledge
Indicates a successful data transfer. The transmitter will release the bus after sending 8 bits of data. Dur-
ing the 9th clock cycle the receiver will pull the SDA line to LOW level to indicate it receive the eight bits
of data.
4.5 Data Transfer
During data transfer the device samples the SDA line on the leading edge of the SCL clock. Therefore, for
proper device operation the SDA line must be stable during the SCL LOW to HIGH transition.
4.6 Device Addressing
To start the communication between two devices, the bus master must initiate a start instruction se-
quence, followed by an eight bit word corresponding to the address of the device it is addressing.
The TDA7514 addresses are: C4 HEX (Section 1 write), C5 HEX (Section 1 read), 8C HEX (Section 2
write), 8D HEX (section 2 read).
The TDA7514 connected to the bus will compare its own hardwired addresses with the slave address be-
ing transmitted, after detecting a START condition.
After this comparison, the TDA7514 will generate an "acknowledge" on the SDA line and will do either a
read or a write operation according to the state of R/W bit.
4.7 Write Operation
Following a START condition the master sends a slave address word with the R/W bit set to "0". The de-
vice will generate an "acknowledge" after this first transmission and will wait for a second word (the sub-
address field).
This 8-bit subaddress field provides an access to any of internal registers. Upon receipt of the word ad-
dress the TDA7514 slave device will respond with an "acknowledge". At this time, all the following words
transmitted will be considered as Data. The internal subaddress can be automatically incremented, ac-
cording to the status of the "Page Mode" bit (Subaddress byte S5).
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