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參數(shù)資料
| 型號(hào)： | TC94A23F |
| 廠商： | Toshiba Corporation |
| 英文描述： | Single-chip CD Processor with Built-in Controller |
| 中文描述： | 單芯片的CD處理器的控制器，內(nèi)置 |
| 文件頁(yè)數(shù)： | 8/20頁(yè) |
| 文件大?。?/td> | 219K |
| 代理商： | TC94A23F |
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TC94A23F
2002-02-06
8
Pin
Number
Symbol
Pin Name
Function and Operation
Remarks
30
P4-1/S12
I/O port 4/serial data
input
31
P4-2
/SI0/SI1/SDA
/serial data
input/output
32
P4-3
/SCK/SCL
/serial clock
input/output
3-bit CMOS I/O port.
Input/output can be set for each bit by
program.
These pins are also used as serial interface
(SIO) circuit input/output pins.
SIO is a serial interface supporting 2-line and
3-line methods. Starting from the MSB or LSB,
4 or 8-bit serial data are output to the SO/SDA
pin, or data on the SI1 and SI2 pins are input
to the device at the clock edge on the
SCK/SCL pin. As the serial operating clock
(SCK/SCL), an internal (450/225/150/75 kHz)
or external clock can be selected. Rising or
falling shift can also be selected. The clock
and data output can be N-channel open drain.
These selections facilitate controlling the LSI
and communications between the controllers.
When SIO interrupts are enabled, an interrupt
is generated as soon as execution of the SIO
completes, and the program jumps to address
4. This is effective for performing serial
communications at high speed.
All SIO inputs incorporate a Schmidt circuit.
SIO and its control can be set by program.
38
TESTC
88
TESTM
Test mode control
input
Input pins for controlling Test mode.
When the pins are at High level, the device is
in Test mode; at Low level, in normal
operation.
Normally, set the pins to Low level or NC
(pull-down resistors are incorporated).
39~42
OT19/
HSO
OT20/SPCK
OT21/SPDA
OT22/COFS
Output port/CD
control signal output
4-bit general-purpose output port.
After system reset, the pins are set to a
Low-level output port.
The pins can be switched to CD control output
pins by program. Setting OT19 to OT22 to 0
switches all four pins to CD control output
pins. Setting OT19 to OT22 and CDIO to 1
enables the pins to be switched as follows
according to the segment data contents of the
S15 and S16 pins:
HSO
: Outputs playback speed mode.
Normal speed: High
Double speed: Low
SPCK: Outputs clock for reading processor
status signal (176.4 kHz).
APCK: Outputs clock for reading processor
status signal.
SPDA: Outputs processor status signal.
COFS: Outputs frame clock for correction
(7.35 kHz).
MV
DD
MV
DD
Input instruction SI0
ON
MV
DD
R
IN2
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