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參數(shù)資料
| 型號： | TC94A23F |
| 廠商： | Toshiba Corporation |
| 英文描述： | Single-chip CD Processor with Built-in Controller |
| 中文描述： | 單芯片的CD處理器的控制器，內(nèi)置 |
| 文件頁數(shù)： | 2/20頁 |
| 文件大?。?/td> | 219K |
| 代理商： | TC94A23F |
TC94A23F
2002-02-06
2
4-bit Microcontroller
Program memory (ROM): 16-bit 8k-step
Data memory (RAM): 4-bit 512-word
Instruction execution time: 1.89/1.78/40 s (all one-word instructions)
Crystal oscillator frequency: 16.9344 MHz/4.5 MHz/75 kHz
Stack level: 8
AD converter: 6-bit 4-channel
LCD driver: 1/4 duty, 1/2 or 1/3 bias method, 72 segments max
LED driver: 4-digit 14-segment (max), also used as LCD driver switched by software
I/O port: CMOS I/O port: 16
N-channel open drain I/O port: 4 (max)
Output-only port: 4 (max), also used as CD processor pins
Input-only port: 4
Timer/counter: 8 bit (INTR, instruction cycle, 100/1 kHz selectable as timer clock)
10, 100, or 500 Hz: internal port
2 Hz: Flip-flop port
Serial interface: Supports 2/3-line method (data length: 4 or 8 bits)
Buzzer: Four types: 0.75, 1, 1.5, and 3 kHz
Four modes: Continuous, Single-Shot, 10 Hz Intermittent, and 10 Hz Intermittent at 1 Hz Interval)
Interrupt: 1 external, 3 internal (CD sub-sync, serial interface, 8-bit timer)
Back-up mode: three types
Clock Stop (crystal oscillator off)
Hardware Wait (crystal oscillator on but CPU in operation)
Software Wait (CPU in intermittent operation)
Reset function: Power-on reset, built-in supply voltage detector (detection voltage 2.5 V typ.)
CD Processor
Reliable sync pattern detection, sync signal protection and interpolation
Built-in EFM decoder and sub code decoder
High-correction capability using cross interleave read Solomon code (CIRC) logical equation
C1 correction: dual
C2 correction: quadruple
Supports variable speeds.
Jitter absorption capability of 6 frames
Built-in 16 KB RAM
Built-in digital output circuit
Built-in L/R independent digital attenuators
Bilingual audio output (Note)
Sub code Q data are read-timing free and can be output in sync with audio data. (Note)
Built-in data slice and analog PLL (adjustment-free VCO used) circuit
Auto adjustment of loop gain, offset, and balance at focus servo and tracking servo
RF gain auto adjustment circuit
Built-in digital equalizer for phase compensation
Supports different pickups using built-in digital equalizer coefficient RAM.
Built-in focus and tracking servo control circuit
Search control supports all modes and realizes high-speed, stable search.
Lens kick and feed kick use speed control method.
Built-in AFC circuit and APC circuit for disc motor CLV servo.
Built-in defect/shock detector
Built-in 8 times oversampling digital filter and 1-bit DA converter.
Note:
Output pins for sub code Q data and audio data are also used as LCD driver pins. The function of the pins
can be switched by program.
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