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參數(shù)資料
| 型號： | TC94A23F |
| 廠商： | Toshiba Corporation |
| 英文描述： | Single-chip CD Processor with Built-in Controller |
| 中文描述： | 單芯片的CD處理器的控制器，內(nèi)置 |
| 文件頁數(shù)： | 4/20頁 |
| 文件大?。?/td> | 219K |
| 代理商： | TC94A23F |
TC94A23F
2002-02-06
4
Block Diagram
P3-3 (ADin3)
RST
TESTM
DV
SL
LO
DV
RL
DV
DD
RO
DV
RR
DV
SR
IN1 (BCKin)
IN2
P4-3 (SCK/SCL)
P4-2 (SI0/SI1/SDA)
TMAX
PDO
P2V
REF
VCOF
SBOK
PV
REF
SBSY
DOUT
OT22 (COFS)
OT21 (SPDA)
OT20 (SPCK)
TESTC
MV
SS
MV
DD
A
S
A
D
R
R
R
F
S
T
T
F
F
D
2
R
S
T
T
R
V
R
HOLD
P4-0 (ADin4/BUZR)
P3-1 (ADin1)
P3-2 (ADin2)
OT19 (
HSO
)
XV
SS
XO
XI
XV
DD
V
DD
V
SS
C
C
C
C
S
P4-1 (SI2)
S
S
S
S
P
P
P
P
LPFN
RFI
SLCO
P3-0
INTR
P2-3 (DATAin)
P2-0 (EMPHin)
P2-1 (
HSO
in)
P2-2 (LRCKin)
LPFO
MXI
MXO
P1-3
P1-0
S
S
X
L
X’tal OSC
Port1
MPX
Clock gene.
CPU clock
Timer
Interrupt
Cont.
Port4
BUZR
AD
Conv.
Serial
Interface
Port3
LCD Driver/Output Port
Port8
Bias
1
ZDET
PWM
CD clock
V
REF
SBSY
DA
SERVO
control
Digital equalizer
Automatic adjustment
circuit
ROM
RAM
16 k SRAM
CLV
servo
V
REF
Synchronous
guarantee EFM
decode
Sub code decoder
Data
slicer
V
REF
PLL
TMAX
VCO
Correction circuit
A
AD
Digital out
Audio out
Micon interface
Data Reg (16 bit)
ROM
(16 8192 Step)
Program
Counter
Stack Reg.
(8Level)
G-Reg.
R/W Buf.
ALU
OT19-22
P
Power on Reset
F/F
Reset
ZDET, CLCK, DATA, SFSY, LRCK, BCK, MBOV, IPF
RAM
(4 512 word)
Instruction
Decoder
SBSY
CLCK, DATA, SFSY,
LRCK, BCK, MBOV, IPF
CD Reset
P2-0~P2-3
IN1
Reset
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