參數(shù)資料
型號: TAS5504PAGG4
廠商: TEXAS INSTRUMENTS INC
元件分類: 消費家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝: GREEN, PLASTIC, TQFP-64
文件頁數(shù): 53/96頁
文件大小: 1216K
代理商: TAS5504PAGG4
Serial Audio Interface Control and Timing
50
SLES123 October 2004
TAS5504
3.6.9 Volume Control
3.6.9.1
Control Signal Parameters Over Recommended Operating Conditions (Unless
Otherwise Noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNITS
Maximum attenuation before mute
Individual volume, master volume or a
combination of both
127
dB
Maximum gain
Individual volume, master volume
18
dB
Maximum volume before the onset of clipping
0-dB input, any modulation limit
0
dB
PSVC range
PSVC enabled
12, 18, or 24
dB
PSVC rate
Fs
PSVC modulation
Single Sided
PSVC quantization
2048
Steps
PSVC PWM modulation limits
PSVC Rangel = 24 dB
6% (120 :
2048)
95% 1944 :
2048
dB
3.7
Serial Audio Interface Control and Timing
3.7.1 I2S Timing
I2S timing uses an LRCLK to define when the data being transmitted is for the left channel and when it is for
the right channel. The LRCLK is low for the left channel and high for the right channel. A bit clock running at
64 × Fs is used to clock in the data. There is a delay of one bit clock from the time the LRCLK signal changes
state to the first bit of data on the data lines. The data is written MSB first and is valid on the rising edge of
bit clock. The TAS5504 masks unused trailing data bit positions.
23 22
SCLK
32 Clks
LRCLK (Note Reversed Phase)
Left Channel
24-Bit Mode
9
8
5
4
1
0
19 18
20-Bit Mode
5
4
1
0
16-Bit Mode
1
0
15 14
MSB
LSB
23 22
SCLK
32 Clks
Right Channel
9
8
5
4
1
0
19 18
5
4
1
0
1
0
15 14
MSB
LSB
2-Channel I2S (Philips Format) Stereo Input
NOTE: All data presented in 2s complement form with MSB first.
Figure 39. I2S Format 64 Fs Format
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