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參數(shù)資料
| 型號： | TAS5504PAGG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | GREEN, PLASTIC, TQFP-64 |
| 文件頁數(shù)： | 41/96頁 |
| 文件大?。?/td> | 1216K |
| 代理商： | TAS5504PAGG4 |
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TAS5504 Controls and Status
39
SLES123 October 2004
TAS5504
Table 28. Volume Ramp Rates in ms
NUMBER OF STEPS
SAMPLE RATE (kHz)
NUMBER OF STEPS
44.1, 88.2, 176.4
32, 48, 96, 192
512
46.44 ms
42.67 ms
1024
92.88 ms
85.33 ms
2048
185.76 ms
170.67 ms
2.3.7 Modulation Index Limit
PWM modulation is a linear function of the audio signal. When the audio signal is 0, the PWM modulation is
50%. When the audio signal increases towards full scale, the PWM modulation increases towards 100%. For
negative signals, the PWM modulations fall below 50% towards 0%.
However, there is a limit to the maximum modulation possible. During the off-time period, the power stage
connected to the TAS5504 output needs to get ready for he next on-time period. The maximum possible
modulation is then set by the power stage requirements. A modulation index of 97.7% is the default setting
of the TAS5504. Default settings can be changed in the Modulation Index Register (0x16).
Note that no change should be made to this register when using Texas Instruments power stages.
2.3.8 Inter-channel Delay
An 8-bit value can be programmed to each of the four PWM inter-channel delay registers to add a delay per
channel from 0 to 255 clock cycles. The delays correspond to cycles of the high-speed internal clock, DCLK.
The default values are shown in Table 29.
Table 29. Inter-Channel Delay Default Values
I2C SUB-ADDRESS
CHANNEL
INTER-CHANNEL DELAY DEFAULT (DCLK PERIODS)
0x1B
1
24
0x1C
2
0
0x21
3
8
0x22
4
+24
This delay is generated in the PWM and can be changed at any time through the serial control interface I2C
registers 0x1B – 0x22. The absolute offset for channel 1 is set in I2C sub-address 0x23.
NOTE:If used correctly, setting the PWM channel delay can optimize the performance of a
pure path digital amplifier system. The setting is based upon the type of backend power device
that is used and the layout. These values are set during initialization using the I2C serial
interface. Unless otherwise noted, use the default values given in Table 29.
2.4
Master Clock and Serial Data Rate Controls
The TAS5504 function only as a receiver of the MCLK (master clock), SCLK (shift clock), and LRCLK (left/right
clock) signals that controls the flow of data on the four serial data interfaces. The 13.5-MHz external crystal
allows the TAS5504 to automatically detect MCLK and the data rate.
The MCLK frequency can be 64 x Fs, 128 x Fs, 196 x Fs, 256 x Fs, 384 x Fs, 512 x Fs, or 768 x Fs.
The TAS5504 operates with the serial data interface signals LRCLK and SCLK synchronized to MCLK.
However, there is no constraint as to the phase relationship of these signals. The TAS5504 accepts a 64 x
Fs SCLK rate and a 1 x Fs LRCLK.
If the phase of SCLK or LRCLK drifts more than ±10 MCLK cycles since the last RESET, the TAS5504 performs
a clock error and resynchronize the clock timing.
The clock and serial data interface have several control parameters:
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TAS5504PAGR | 功能描述:音頻 DSP 4 Ch Digital Audio PWM Processor RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| TAS5504PAGRG4 | 功能描述:音頻 DSP 4 Ch Digital Audio PWM Processor RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| TAS5508 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:8 Channel Digital Audio PWM Processor |
| TAS5508-5121K8EVM | 功能描述:音頻 IC 開發(fā)工具 TAS5508-TAS5121K8 Eval Mod RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V |
| TAS5508-5122C6EVM | 功能描述:音頻 IC 開發(fā)工具 TAS5508-5122C6 Eval Mod RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V |
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