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參數(shù)資料
| 型號： | T35L3232B |
| 廠商： | TM Technology, Inc. |
| 英文描述： | 32K x 32 SRAM |
| 中文描述： | 32K的× 32的SRAM |
| 文件頁數(shù)： | 7/19頁 |
| 文件大?。?/td> | 261K |
| 代理商： | T35L3232B |
TE
CH
tm
PIPELINE READ/WRITE TIMING
Preliminary T35L3232B
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
P. 15
Publication Date: FEB. 2000
Revision:0.A
A4
High-Z
BURST READ
CLK
ADSC
ADSP
ADDRESS
BWE
BW 1- B W4
tKC
tKH
tKL
tADSStADSH
DON'T CARE
UNDEFINED
tAStAH
tWStWH
tCEStCEH
tDH
tKQ
tOELZ
tOEHZ
tDS
tKQ
tKQLZ
Single WRITE
Q(A1)
Q(A2)
Q(A3)
Q(A4)
Q(A4+1)
Q(A4+3)
Q(A4+2)
A5
A3
A1
(NOTE1)
CE
(NO T E 2)
ADV
O E
D
A2
A6
Q
High-Z
D(A3)
D(A5)
D(A6)
Back-to-Back READs
Pass-through
READ
Back-to-Back
WRITEs
Note:
1. Q(A4) refers to output from address A4. Q (A4 + 1) refers to output from the next internal burst
address following A4.
2.
CE2
and CE2 have timing identical to CE . On this diagram, when CE is LOW,
CE2
is
LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW.
3. The data bus (Q) remains in High-Z following a WRITE cycle unless an
ADSP
,
ADSC
or
ADV
cycle is performed.
4.
GW
is HIGH.
5. Back-to-back READs may be controlled by either
ADSP
or
ADSC
.
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| T35L3232B-4T | 32K x 32 SRAM |
| T35L6432A | 64K x 32 SRAM |
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相關代理商/技術參數(shù) |
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|---|---|
| T35L3232B-3.8Q | 制造商:TMT 制造商全稱:TMT 功能描述:32K x 32 SRAM |
| T35L3232B-4T | 制造商:TMT 制造商全稱:TMT 功能描述:32K x 32 SRAM |
| T35L6432A | 制造商:TMT 制造商全稱:TMT 功能描述:64K x 32 SRAM |
| T35L6432A-5Q | 制造商:TMT 制造商全稱:TMT 功能描述:64K x 32 SRAM |
| T35L6432A-5T | 制造商:TMT 制造商全稱:TMT 功能描述:64K x 32 SRAM |
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