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參數(shù)資料
| 型號： | T35L3232B |
| 廠商： | TM Technology, Inc. |
| 英文描述： | 32K x 32 SRAM |
| 中文描述： | 32K的× 32的SRAM |
| 文件頁數(shù)： | 11/19頁 |
| 文件大小： | 261K |
| 代理商： | T35L3232B |
TE
CH
tm
Preliminary T35L3232B
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
P. 4
Publication Date: FEB. 2000
Revision:0.A
PIN DESCRIPTIONS
PINS
SYM.
TYPE
DESCRIPTION
32-37, 44-48,
81, 82, 99,
100,
A0-A14
Input-
Synchronous
Addresses: These inputs are registered and must meet the setup and
hold times around the rising edge of CLK. The burst counter
generates internal addresses associated with A0 and A1, during
burst cycle and wait cycle.
Byte Writes: A byte write is LOW for a WRITE cyle and HIGH for
a READ cycle.
BW1
controls DQ1-DQ8.
BW2
controls DQ9-
DQ16.
BW3
controls DQ17-DQ24.
BW4
controls DQ25-DQ32.
Data I/O are high impedance if either of these inputs are LOW ,
conditioned by
BWE
being LOW.
Write Enable: This active LOW input gates byte write operations
and must meet the setup and hold times around the rising edge of
CLK.
93-96
BW1
BW2
BW3
BW4
Input-
Synchronous
87
BWE
Input-
Synchronous
88
GW
Input-
Synchronous
Global Write: This active LOW input allows a full 32-bit WRITE to
occur independent of the
BWE
and
BWn
the setup and hold times around the rising edge of CLK.
lines and must meet
89
CLK
Input-
Synchronous
Clock: This signal registers the addresses, data, chip enables,
writecontrol and burst control inputs on its rising edge. All
synchronous inputs must meet setup and hold times around the
clock's rising edge.
Synchronous Chip Enable: This active LOW input is used to enable
the device and conditions internal use of
ADSP
. This input is
sampled only when a new external address is loaded.
98
CE
Input-
Synchronous
92
CE2
Input-
Synchronous
Synchronous Chip Enable: This active LOW input is used to enable
the device. This input is sampled only when a new external address
is loaded. This input can be used for memory depth expansion.
97
CE2
Input-
Synchronous
Synchronous Chip Enable: This active HIGH input is used to enable
the device. This input is sampled only when a new external address
is loaded. This input can be used for memory depth expansion.
86
OE
Input
Output enable: This active LOW asynchronous input enables the
data output drivers.
83
ADV
Input-
Synchronous
Address Advance: This active LOW input is used to control the
internal burst counter. A HIGH on this pin generates wait cycle
(no address advance).
Address Status Processor: This active LOW input, along with
CE
being LOW, causes a new external address to be registered and a
READ cycle is initiated using the new address.
84
ADSP
Input-
Synchronous
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PDF描述 |
|---|---|
| T35L3232B-3.8Q | 32K x 32 SRAM |
| T35L3232B-4T | 32K x 32 SRAM |
| T35L6432A | 64K x 32 SRAM |
| T35L6432A-5Q | 64K x 32 SRAM |
| T35L6432A-5T | 64K x 32 SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| T35L3232B-3.8Q | 制造商:TMT 制造商全稱:TMT 功能描述:32K x 32 SRAM |
| T35L3232B-4T | 制造商:TMT 制造商全稱:TMT 功能描述:32K x 32 SRAM |
| T35L6432A | 制造商:TMT 制造商全稱:TMT 功能描述:64K x 32 SRAM |
| T35L6432A-5Q | 制造商:TMT 制造商全稱:TMT 功能描述:64K x 32 SRAM |
| T35L6432A-5T | 制造商:TMT 制造商全稱:TMT 功能描述:64K x 32 SRAM |
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