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參數(shù)資料
| 型號： | T35L3232B-3.8Q |
| 廠商： | TM Technology, Inc. |
| 英文描述： | 32K x 32 SRAM |
| 中文描述： | 32K的× 32的SRAM |
| 文件頁數(shù)： | 1/19頁 |
| 文件大小： | 261K |
| 代理商： | T35L3232B-3.8Q |
TE
CH
tm
SYNCHRONOUS
BURST SRAM
Preliminary T35L3232B
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
P. 1
Publication Date: FEB. 2000
Revision:0.A
32K x 32 SRAM
Pipeline and Flow-Through Burst Mode
FEATURES
E
FT
pin for user configurable pipeline or
flow-through operation.
E
Fast Access times:
- Pipeline – 3.8 / 4 / 4.5 ns
- Flow-through – 9 / 10 / 11ns
E
Single 3.3V +0.3V/-0.165V power supply
E
Common data inputs and data outputs
E
Individual BYTE WRITE ENABLE and
GLOBAL WRITE control
E
Three chip enables for depth expansion and
address pipelining
E
Clock-controlled and registered address, data
I/Os and control signals
E
Internally self-timed WRITE CYCLE
E
Burst control pins ( interleaved or linear burst
sequence)
E
High 30pF output drive capability at rated
access time
E
SNOOZE MODE for reduced power standby
E
Burst Sequence :
- Interleaved (MODE=NC or VCC)
- Li nea
r (MODE=GND)
OPTIONS
MARKING
-3.8
Access
time
3-1-1-1
Cycle
time
Access
time
through
2-1-1-1
time
Package
100-pin QFP
100-pin TQFP
Part Number Examples
PART NO.
T35L3232B-3.8Q
T35L3232B-4T
-4
-4.5
3.8ns
4ns
4.5ns
Pipeline
6.6ns
7.5ns
8.5ns
9ns
10ns
11ns
Flow-
Cycle
10.5ns
15ns
15ns
Q
T
Pkg.
Q
T
GENERAL DESCRIPTION
The Taiwan Memory Technology Synchronous
Burst RAM family employs high-speed, low power
CMOS design using advanced triple-layer polysilicon,
double-layer metal technology. Each memory cell
consists of four transistors and two high valued resistors.
The T35L3232B SRAM integrates 32,768 x 32
bits SRAM cells with advanced synchronous peripheral
circuitry and a 2-bit counter for internal burst operation.
All synchronous inputs are gated by registers controlled
by a positive-edge-triggered clock input (CLK). The
synchronous inputs include all addresses, all data inputs,
address-pipelining
chip enable (
CE
), depth-
expansion chip enables (
CE2
and CE2), burst control
inputs (
ADSC
,
ADSP
, and
ADV
), write enables
(
BW1
,
BW2
,
BW3
,
BW4
, and
BWE
), and
global write (
GW
).
Asynchronous inputs include the output enable
(
OE
), Snooze enable (ZZ) and burst mode control
(MODE). The data outputs (Q), enabled by
OE
, are
also asynchronous.
Addresses and chip enables are registered with
either address status processor (
ADSP
) or address
status controller (
ADSC
) input pins. Subsequent burst
addresses can be internally generated as controlled by
the burst advance pin (
ADV
).
Address and write controls are registered on-chip
to initiate self-timed WRITE cycle. WRITE cycles
can be one to four bytes wide as controlled by the write
control inputs. Individual byte write
allows individual byte to be written.
BW1
controls
DQ1-DQ8.
BW2
controls DQ9-DQ16.
controls DQ17-DQ 24.
BW4
controls DQ25-DQ32.
BW1
,
BW2
,
BW3
, and
BW4
can be active only
with
BWE
being LOW.
GW
being LOW causes
all bytes to be written.
capability allows written data available at the output for
the immediately next READ cycle. This device also
incorporates pipelined enable circuit for easy depth
expansion without penalizing system performance.
BW3
WRITE pass-through
相關PDF資料 |
PDF描述 |
|---|---|
| T35L3232B-4T | 32K x 32 SRAM |
| T35L6432A | 64K x 32 SRAM |
| T35L6432A-5Q | 64K x 32 SRAM |
| T35L6432A-5T | 64K x 32 SRAM |
| T35L6432B | 64K x 32 SRAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| T35L3232B-4T | 制造商:TMT 制造商全稱:TMT 功能描述:32K x 32 SRAM |
| T35L6432A | 制造商:TMT 制造商全稱:TMT 功能描述:64K x 32 SRAM |
| T35L6432A-5Q | 制造商:TMT 制造商全稱:TMT 功能描述:64K x 32 SRAM |
| T35L6432A-5T | 制造商:TMT 制造商全稱:TMT 功能描述:64K x 32 SRAM |
| T35L6432B | 制造商:TMT 制造商全稱:TMT 功能描述:64K x 32 SRAM |
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