TE
CH
tm
Preliminary T35L3232B
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
P.9
Publication Date: FEB. 2000
Revision:0.A
AC ELECTRICAL CHARACTERISTICS
(Note 5)
(0
°
C
≤
TA
≤
70
°
C;VCC=3.3V +0.3V/-0.165V)
-3.8
DESCRIPTION
SYM.
MIN MAX MIN MAX MIN MAX
Clock(pipeline)
Clock cycle time
tKC
6.6
Clock to output valid
tKQ
Clock to output invalid
tKQX
1.5
Clock to output in Low-Z
tKQLZ
1.5
Clock(flow-through)
Clock cycle time
tKC
10.5
Clock to output valid
tKQ
Clock to output invalid
tKQX
3
Clock to output in Low-Z
tKQLZ
3
Output Times
Clock HIGH time
tKH
1.8
Clock LOW time
tKL
1.8
Clock to output in High-Z
tKQHZ
OE to output valid
tOEQ
OE to output in Low-Z
tOELZ
0
OE to output in High-Z
tOEHZ
Setup Times
Address
tAS
1.7
tADSS
1.7
Address Advance (ADV)
tAAS
1.7
Byte Write Enables
(BW1~BW4,BWE ,GW)
Data-in
tDS
1.7
Chip Enables(CE ,CE2,CE2)
tCES
1.7
Hold Times
Address
tAH
0.5
Address Status(ADSC,ADSP )
tADSH
0.5
Address Advance (ADV)
tAAH
0.5
Byte Write Enables
(BW1~BW4,BWE ,GW)
Data-in
tDH
0.5
Chip Enables(CE ,CE2,CE2)
tCEH
0.5
-4
-4.5
UNITS
NOTES
7.5
8.5
ns
3.8
4
4.5
2
2
2
2
ns
ns
15
15
ns
9.0
10
11
3
3
3
3
ns
ns
1.9
1.9
2.0
2.0
ns
ns
ns
ns
ns
ns
6, 7
6, 7
9
6, 7
6, 7
5
5
5
5
5
5
0
0
5
5
5
2.0
2.0
ns
8, 10
Address Status(ADSC,ADSP )
2.0
2.0
ns
8, 10
2.0
2.0
ns
8, 10
tWS
1.7
2.0
2.0
ns
8, 10
2.0
2.0
ns
8, 10
2.0
2.0
ns
8, 10
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
8, 10
8, 10
8, 10
8, 10
tWH
0.5
0.5
0.5
0.5
0.5
ns
ns
8, 10
8, 10