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參數(shù)資料
| 型號： | T35L3232B-4T |
| 廠商： | TM Technology, Inc. |
| 英文描述： | 32K x 32 SRAM |
| 中文描述： | 32K的× 32的SRAM |
| 文件頁數(shù)： | 8/19頁 |
| 文件大?。?/td> | 261K |
| 代理商： | T35L3232B-4T |
TE
CH
tm
FLOW-THROUGH READ/WRITE TIMING
Preliminary T35L3232B
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
P. 16
Publication Date: FEB. 2000
Revision:0.A
Note:
1. Q(A4) refers to output from address A4. Q (A4 + 1) refers to output from the next internal burst
address following A4.
2.
CE2
and CE2 have timing identical to CE . On this diagram, when CE is LOW,
CE2
is
LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW.
3. The data bus (Q) remains in High-Z following a WRITE cycle unless an
ADSP
,
ADSC
or
ADV
cycle is performed.
4.
GW
is HIGH.
5. Back-to-back READs may be controlled by either
ADSP
or
ADSC
.
A 4
BURST READ
CLK
ADSC
ADSP
ADDRESS
BW E
BW1-BW4
(NOTE4)
tKC
tKH
tKL
tADSStADSH
DON'T CARE
UNDEFINED
tAS
tAH
tW S
tW H
tCEStCEH
tDH
tKQ
tOELZ
tOEHZ
tDS
Single W RITE
Q(A1)
Q(A2)
Q(A4)
Q(A4+1)
Q(A4+3)
Q(A4+2)
A 5
A 3
A 1
(NOTE1)
CE
(NOTE2)
ADV
O E
D
A 2
A 6
Q
High-Z
D(A3)
D(A5)
D(A6)
Back-to-Back READs
Back-to-Back
W RITEs
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| T35L6432A | 64K x 32 SRAM |
| T35L6432A-5Q | 64K x 32 SRAM |
| T35L6432A-5T | 64K x 32 SRAM |
| T35L6432B | 64K x 32 SRAM |
| T35L6432B-10Q | 64K x 32 SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| T35L6432A | 制造商:TMT 制造商全稱:TMT 功能描述:64K x 32 SRAM |
| T35L6432A-5Q | 制造商:TMT 制造商全稱:TMT 功能描述:64K x 32 SRAM |
| T35L6432A-5T | 制造商:TMT 制造商全稱:TMT 功能描述:64K x 32 SRAM |
| T35L6432B | 制造商:TMT 制造商全稱:TMT 功能描述:64K x 32 SRAM |
| T35L6432B-10Q | 制造商:TMT 制造商全稱:TMT 功能描述:64K x 32 SRAM |
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