參數(shù)資料
型號(hào)： T35L3232B-4T
廠(chǎng)商： TM Technology, Inc.
英文描述： 32K x 32 SRAM
中文描述： 32K的× 32的SRAM
文件頁(yè)數(shù)： 4/19頁(yè)
文件大?。?/td> 261K
代理商： T35L3232B-4T
TE
CH
tm
PIPELINE READ TIMING
Preliminary T35L3232B
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
P. 12
Publication Date: FEB. 2000
Revision:0.A
High-Z
BURST READ
CLK
ADSC
ADSP
ADDRESS
GW, BWE,
BW 1- BW4
tKC
tKH
tKL
tADSStADSH
DON'T CARE
UNDEFINED
tADSS
tADSH
tAStAH
tWStWH
tCEStCEH
tAAS
tAAH
tOEQ
tOELZ
tKQX
tOEHZ
tKQ
tKQHZ
tKQX
tKQ
tKQLZ
Single READ
(NOTE3)
Q(A1)
Q(A2)
Q(A2+1)
Q(A2+2)
Q(A2+3)
Q(A2+1)
Burst wraps around
to its inital state.
ADV suspends burst.
Burst continued with
new base address.
Q(A2)
A3
A2
A1
(NOTE1)
Deselect cycle.
CE
(NOT E 2)
ADV
O E
Q
Q(A3)
Note:
1. Q(A2) refers to output from address A2. Q (A2 + 1) refers to output from the next internal burst
address following A2.
2.
CE2
and CE2 have timing identical to
CE
. On this diagram, when
CE
is LOW,
CE2
is LOW
and CE2 is HIGH. When
CE
is HIGH,
CE2
is HIGH and CE2 is LOW.
3. Timing is shown assuming that the device was not enabled before entering into this sequence.
OE
does not cause Q to be driven until after the following clock rising edge.
相關(guān)PDF資料
PDF描述
T35L6432A 64K x 32 SRAM
T35L6432A-5Q 64K x 32 SRAM
T35L6432A-5T 64K x 32 SRAM
T35L6432B 64K x 32 SRAM
T35L6432B-10Q 64K x 32 SRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
T35L6432A 制造商:TMT 制造商全稱(chēng):TMT 功能描述:64K x 32 SRAM
T35L6432A-5Q 制造商:TMT 制造商全稱(chēng):TMT 功能描述:64K x 32 SRAM
T35L6432A-5T 制造商:TMT 制造商全稱(chēng):TMT 功能描述:64K x 32 SRAM
T35L6432B 制造商:TMT 制造商全稱(chēng):TMT 功能描述:64K x 32 SRAM
T35L6432B-10Q 制造商:TMT 制造商全稱(chēng):TMT 功能描述:64K x 32 SRAM
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