參數(shù)資料
型號(hào): T35L3232B-4T
廠商: TM Technology, Inc.
英文描述: 32K x 32 SRAM
中文描述: 32K的× 32的SRAM
文件頁(yè)數(shù): 6/19頁(yè)
文件大?。?/td> 261K
代理商: T35L3232B-4T
TE
CH
tm
WRITE TIMING
Preliminary T35L3232B
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
P. 14
Publication Date: FEB. 2000
Revision:0.A
BURST WRITE
CLK
ADSC
High-Z
ADSP
ADDRESS
BWE,
BW 1- BW4
tKC
tKH
tKL
tADSStADSH
DON'T CARE
UNDEFINED
tAStAH
tWStWH
tCEStCEH
tAAStAAH
tOEHZ
tDS
tDH
Single WRITE
(NOTE3)
D(A1)
D(A2)
D(A2+1)
D(A2+2)
D(A2+3)
D(A3+1)
D(A3)
A3
A2
A1
(NOTE1)
CE
(N O T E 2)
ADV
O E
D
ADSC extends btADSStADSH
tADSStADSH
G W
tWStWH
D(A2+1)
D(A3+2)
BURST READ
Extended BURST WRITE
Q
ADV suspnds burst.
(NOTE4)
(NOTE5)
BYTE WRITE signals are
ignored for first cycle when
ADSP initialtes burst.
Note:
1. Q(A2) refers to output from address A2. Q (A2 + 1) refers to output from the next internal burst
address following A2.
2.
CE2
and CE2 have timing identical to
CE
. On this diagram, when
CE
is LOW ,
CE2
is
LOW and CE2 is HIGH. When
CE
is HIGH ,
CE2
is HIGH and CE2 is LOW.
3.
OE
must be HIGH before the input data setup and hold HIGH throughout the data hold time.
This prevents input/output data contention for the time period to the byte write enable inputs being
sampled.
4.
ADV
must be HIGH to permit a WRITE to the loaded address.
5. Full width WRITE can be initiated by GW LOW or GW HIGH and BWE ,BW1-BW4
LOW.
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