- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄361342 > T35L3232B-4T (TM Technology, Inc.) 32K x 32 SRAM PDF資料下載
參數(shù)資料
| 型號： | T35L3232B-4T |
| 廠商： | TM Technology, Inc. |
| 英文描述： | 32K x 32 SRAM |
| 中文描述： | 32K的× 32的SRAM |
| 文件頁數(shù)： | 5/19頁 |
| 文件大?。?/td> | 261K |
| 代理商： | T35L3232B-4T |
TE
CH
tm
FLOW-THROUGH READ TIMING
Preliminary T35L3232B
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
P. 13
Publication Date: FEB. 2000
Revision:0.A
Note:
1. Q(A2) refers to output from address A2. Q (A2 + 1) refers to output from the next internal burst
address following A2.
2.
CE2
and CE2 have timing identical to
CE
. On this diagram, when
CE
is LOW,
CE2
is LOW
and CE2 is HIGH. When
CE
is HIGH,
CE2
is HIGH and CE2 is LOW.
3. Timing is shown assuming that the device was not enabled before entering into this sequence.
OE
does not cause Q to be driven until after the following clock rising edge.
4. Output are disabled tKQHZ after diselect.
High-Z
BURST READ
CLK
ADSC
ADSP
ADDRESS
GW, BWE,
BW1-BW4
tKC
tKH
tKL
tADSStADSH
DON'T CARE
UNDEFINED
tADSS
tADSH
tAS
tAH
tW S
tW H
tCEStCEH
tAAS
tAAH
tOEQ
tKQX
tOELZ
tOEHZ
tKQ
tKQHZ
tKQ
tKQLZ
Single READ
Q(A1)
Q(A2)
Q(A2+1)
Q(A2+2)
Q(A2+3)
Q(A2+1)
Burst wraps around to
its inital state.
ADV suspends burst.
Q(A2)
A2
A 1
(NOTE1)
CE
(NOTE2)
ADV
O E
Q
Deselect Cycle
(NOTE 4)
Q(A2+2)
相關PDF資料 |
PDF描述 |
|---|---|
| T35L6432A | 64K x 32 SRAM |
| T35L6432A-5Q | 64K x 32 SRAM |
| T35L6432A-5T | 64K x 32 SRAM |
| T35L6432B | 64K x 32 SRAM |
| T35L6432B-10Q | 64K x 32 SRAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| T35L6432A | 制造商:TMT 制造商全稱:TMT 功能描述:64K x 32 SRAM |
| T35L6432A-5Q | 制造商:TMT 制造商全稱:TMT 功能描述:64K x 32 SRAM |
| T35L6432A-5T | 制造商:TMT 制造商全稱:TMT 功能描述:64K x 32 SRAM |
| T35L6432B | 制造商:TMT 制造商全稱:TMT 功能描述:64K x 32 SRAM |
| T35L6432B-10Q | 制造商:TMT 制造商全稱:TMT 功能描述:64K x 32 SRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復。