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參數(shù)資料
| 型號(hào)： | SX28AC/SSU |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), I2C BUS CONTROLLER, PDSO28 |
| 封裝： | GREEN, PLASTIC, SSOP-28 |
| 文件頁(yè)數(shù)： | 31/48頁(yè) |
| 文件大?。?/td> | 772K |
| 代理商： | SX28AC/SSU |
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2005 Ubicom, Inc. All rights reserved.
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SX20AC/SX28AC
CALL addr8
Call Subroutine:
top-of-stack = program counter + 1
PC(7:0) = addr8
program counter (8) = 0
program counter (10:9) = PA1:PA0
23
1001 kkkk kkkk
none
JMP addr9
Jump to Address:
PC(7:0) = addr9(7:0)
program counter (8) = addr9(8)
program counter (10:9) = PA1:PA0
23
101k kkkk kkkk
none
NOP
No Operation
11
0000 0000 0000
none
RET
Return from Subroutine
(program counter = top-of-stack)
23
0000 0000 1100
none
RETP
Return from Subroutine Across Page Boundary
(PA1:PA0 = top-of-stack (10:9) and
program counter = top-of-stack)
23
0000 0000 1101
PA1, PA0
RETI
Return from Interrupt (restore W, STATUS,
FSR, and program counter from shadow regis-
ters)
23
0000 0000 1110
all
STATUS,
except
TO, PD
RETIW
Return from Interrupt and add W to RTCC (re-
store W, STATUS, FSR, and program counter
from shadow registers; and add W to RTCC)
23
0000 0000 1111
all
STATUS,
except
TO, PD
RETW lit
Return from Subroutine with Literal in W
(W = lit and program counter = top-of-stack)
23
1000 kkkk kkkk
none
System Control Instructions
BANK addr8
Load Bank Number into FSR(7:5)
FSR(7:5) = addr8(7:5)
11
0000 0001 1nnn
none
IREAD
Read Word from Instruction Memory Flash.
Flash Address read: {upper 4 bits of address =
lower 4 bits of MODE, lower 8 bits of address =
W register}. The 12 data bits from Flash are
copied into these same 12 bits of MODE:W.
14
0000 0100 0001
none
PAGE addr12
Load Page Number into STATUS(7:5)
STATUS(7:5) = addr12(11:9)
11
0000 0001 0nnn PA1, PA0
SLEEP
Power Down Mode
WDT = 00h, TO = 1, stop oscillator
(PD = 0, clears prescaler if assigned)
11
0000 0000 0011
TO, PD
Table 16-1. The SX Instruction Set (Continued)
Mnemonic,
Operands
Description
Cycles
(Compatible)
Cycles
(Turbo)
Opcode
Bits
Affected
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| SY100EP11UZITR | 100E SERIES, LOW SKEW CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| SY100EP195VTCTR | ACTIVE DELAY LINE, COMPLEMENTARY OUTPUT, PQFP32 |
| SY100EP195VTG | ACTIVE DELAY LINE, COMPLEMENTARY OUTPUT, PQFP32 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SX28AD100-I/DP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Configurable Communications Controllers with EE/Flash Program Memory, In-System Programming Capability and On-Chip Debug |
| SX28AD100-I/PQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Configurable Communications Controllers with EE/Flash Program Memory, In-System Programming Capability and On-Chip Debug |
| SX28AD100-I/SO | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Configurable Communications Controllers with EE/Flash Program Memory, In-System Programming Capability and On-Chip Debug |
| SX28AD100-I/SS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Configurable Communications Controllers with EE/Flash Program Memory, In-System Programming Capability and On-Chip Debug |
| SX28AD100-I/TQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Configurable Communications Controllers with EE/Flash Program Memory, In-System Programming Capability and On-Chip Debug |
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