- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98149 > SX28AC/SSU 2 CHANNEL(S), I2C BUS CONTROLLER, PDSO28 PDF資料下載
參數(shù)資料
| 型號： | SX28AC/SSU |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), I2C BUS CONTROLLER, PDSO28 |
| 封裝： | GREEN, PLASTIC, SSOP-28 |
| 文件頁數(shù)： | 21/48頁 |
| 文件大小： | 772K |
| 代理商： | SX28AC/SSU |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁當前第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁
2005 Ubicom, Inc. All rights reserved.
- 28 -
www.ubicom.com
SX20AC/SX28AC
Figure 12-3 shows the on-chip Power-On Reset
sequence where the MCLR and Vdd pins are tied
together. The Vdd signal is stable before the DRT time-
out period expires. In this case, the device will receive a
proper reset. However, Figure 12-4 depicts a situation
where Vdd rises too slowly. In this scenario, the DRT will
time-out prior to Vdd reaching a valid operating voltage
level (Vdd min). This means the device will come out of
reset and start operating with the supply voltage not at a
valid level. In this situation, it is recommended that you
use the external RC circuit shown in Figure 12-5. The RC
delay should exceed the time period it takes Vdd to reach
a valid operating voltage.
Note 1: The external Power-On Reset circuit is required
only if Vdd power-up is too slow. The diode D helps dis-
charge the capacitor quickly when Vdd powers down.
Note 2: R < 40 k
is recommended to make sure that
voltage drop across R does not violate the device electri-
cal specifications.
Note 3: R1 = 100
to 1k will limit any current flowing
into MCLR from external capacitor C. This helps prevent
MCLR pin breakdown due to Electrostatic Discharge
(ESD) or Electrical Overstress (EOS).
13.0 BROWN-OUT DETECTOR
The on-chip brown-out detection circuitry resets the
device when Vdd dips below the specified brown-out volt-
age. The device is held in reset as long as Vdd stays
below the brown-out voltage. The device will come out of
reset when Vdd rises above the brown-out voltage. The
brown-out level is preset to approximately 4.2V at the
factory. See the FUSEX word register, BOR0 and BOR1
bits, for details.
Figure 12-3. Time-out Sequence on Power-up
(MCLR tied to Vdd): Fast Vdd Rise Time
Figure 12-4. Time-out Sequence on Power-up
(MCLR tied to Vdd): Slow Rise Time
Vdd
MCLR
POR
drt_time_out
RESET
Tdrt
Vdd
MCLR
POR
drt_time_out
RESET
Tdrt
V1
Figure 12-5. External Power-On Reset Circuit
(For Slow Vdd Power-up)
dd
R
C
MCLR
D
R1
相關PDF資料 |
PDF描述 |
|---|---|
| SY100EP11UZITR | 100E SERIES, LOW SKEW CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| SY100EP195VTCTR | ACTIVE DELAY LINE, COMPLEMENTARY OUTPUT, PQFP32 |
| SY100EP195VTG | ACTIVE DELAY LINE, COMPLEMENTARY OUTPUT, PQFP32 |
| SY100EP196VTCTR | ACTIVE DELAY LINE, COMPLEMENTARY OUTPUT, PQFP32 |
| SY100EP196VTC | ACTIVE DELAY LINE, COMPLEMENTARY OUTPUT, PQFP32 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SX28AD100-I/DP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Configurable Communications Controllers with EE/Flash Program Memory, In-System Programming Capability and On-Chip Debug |
| SX28AD100-I/PQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Configurable Communications Controllers with EE/Flash Program Memory, In-System Programming Capability and On-Chip Debug |
| SX28AD100-I/SO | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Configurable Communications Controllers with EE/Flash Program Memory, In-System Programming Capability and On-Chip Debug |
| SX28AD100-I/SS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Configurable Communications Controllers with EE/Flash Program Memory, In-System Programming Capability and On-Chip Debug |
| SX28AD100-I/TQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Configurable Communications Controllers with EE/Flash Program Memory, In-System Programming Capability and On-Chip Debug |
發(fā)布緊急采購，3分鐘左右您將得到回復。