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參數(shù)資料
| 型號： | SX28AC/SSU |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), I2C BUS CONTROLLER, PDSO28 |
| 封裝： | GREEN, PLASTIC, SSOP-28 |
| 文件頁數(shù)： | 27/48頁 |
| 文件大?。?/td> | 772K |
| 代理商： | SX28AC/SSU |
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2005 Ubicom, Inc. All rights reserved.
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www.ubicom.com
SX20AC/SX28AC
15.12 Subroutine Operation
15.12.1 Push Operation
When a subroutine is called, the return address is
pushed onto the subroutine stack. Specifically, each
address in the stack is moved to the next lower level in
order to make room for the new address to be stored.
Stack 1 receives the contents of the program counter.
Stack 8 is overwritten with what was in Stack 7. The con-
tents of stack 8 are lost.
15.12.2 Pop Operation
When a return instruction is executed the subroutine
stack is popped. Specifically, the contents of Stack 1 are
copied into the program counter and the contents of each
stack level are moved to the next higher level. For exam-
ple, Stack 1 receives the contents of Stack 2, etc., until
Stack 7 is overwritten with the contents of Stack 8. Stack
8 is left unchanged, so the contents of Stack 8 are dupli-
cated in Stack 7.
15.13 Comparison and Conditional Branch
Instructions
The instruction set includes instructions such as DECSZ
fr (decrement file register and skip if zero), INCSZ fr
(increment file register and skip if zero), SNB bit (bit test
file register and skip if bit clear), and SB bit (bit test file
register and skip if bit set). These instructions will cause
the next instruction to be skipped if the tested condition is
true. If a skip instruction is immediately followed by a
PAGE or BANK instruction (and the tested condition is
true) then two instructions are skipped and the operation
consumes three cycles. This is useful for conditional
branching to another page where a PAGE instruction pre-
cedes a JMP. If several PAGE and BANK instructions
immediately follow a skip instruction then they are all
skipped plus the next instruction and a cycle is consumed
for each.
PC<10:0>
STACK 1
STACK 2
STACK 3
STACK 4
STACK 5
STACK 6
STACK 7
STACK 8
PC<10:0>
STACK 1
STACK 2
STACK 3
STACK 4
STACK 5
STACK 6
STACK 7
STACK 8
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SY100EP11UZITR | 100E SERIES, LOW SKEW CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| SY100EP195VTCTR | ACTIVE DELAY LINE, COMPLEMENTARY OUTPUT, PQFP32 |
| SY100EP195VTG | ACTIVE DELAY LINE, COMPLEMENTARY OUTPUT, PQFP32 |
| SY100EP196VTCTR | ACTIVE DELAY LINE, COMPLEMENTARY OUTPUT, PQFP32 |
| SY100EP196VTC | ACTIVE DELAY LINE, COMPLEMENTARY OUTPUT, PQFP32 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SX28AD100-I/DP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Configurable Communications Controllers with EE/Flash Program Memory, In-System Programming Capability and On-Chip Debug |
| SX28AD100-I/PQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Configurable Communications Controllers with EE/Flash Program Memory, In-System Programming Capability and On-Chip Debug |
| SX28AD100-I/SO | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Configurable Communications Controllers with EE/Flash Program Memory, In-System Programming Capability and On-Chip Debug |
| SX28AD100-I/SS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Configurable Communications Controllers with EE/Flash Program Memory, In-System Programming Capability and On-Chip Debug |
| SX28AD100-I/TQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Configurable Communications Controllers with EE/Flash Program Memory, In-System Programming Capability and On-Chip Debug |
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