- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄381127 > STW81100ATR (意法半導(dǎo)體) MULTI-BAND RF FREQUENCY SYNTHESIZER WITH INTEGRATED VCOS PDF資料下載
參數(shù)資料
| 型號(hào)： | STW81100ATR |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | MULTI-BAND RF FREQUENCY SYNTHESIZER WITH INTEGRATED VCOS |
| 中文描述： | 多波段射頻頻率合成器帶有集成的VCO |
| 文件頁數(shù)： | 14/23頁 |
| 文件大?。?/td> | 915K |
| 代理商： | STW81100ATR |
STW81100
14/23
7.8.3 VCO Voltage Amplitude Control
The bits A0 and A1 control the voltage swing of the VCO. The following table gives the voltage level ex-
pected on the resonator nodes.
Table 9.
8
Data transmission from microprocessor to the STW81100 takes place through the 2 wires (SDA and SCL)
I
2
C-BUS interface. The STW81100 is always a slave device.
The I
2
C-bus protocol defines any device that sends data on to the bus as a transmitter and any device that
reads the data as receiver. The device that controls the data transfer is known as the Master and the oth-
ers as the slave. The master will always initiate the transfer and will provide the serial clock for synchro-
nization.
I
2
C bus interface
8.1 General Features
8.1.1 Power ON Reset
The device at Power ON is able to configure itself to a fixed configuration, with all programmable bits set
to factory default setting.
8.1.2 Data Validity
Data changes on the SDA line must only occur when the SCL is LOW. SDA transitions while the clock is
HIGH are used to identify START or STOP condition.
Figure 17.
8.1.3 START condition
A Start condition is identified by a HIGH to LOW transition of the data bus SDA while the clock signal SCL
is stable in the HIGH state. A Start condition must precede any command for data transfer.
Code A[1:0]
Differential output voltage (Vp)
00
1.1
01
1.3
10
1.9
11
2.1
SDA
SCL
ALLOWED
VALID
CHANGE
DATA
DATA LINE
STABLE DATA
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| STY140NS10 | CAP 0.22UF 100V 10% X7R AXIAL TR-14 |
| STY16NA90 | N-Channel 900V-0.5Ω-16A- Max247 Extremely Low Gate Charge Power MOSFET(N溝道功率MOSFET) |
| STY34NB50 | N-Channel 500V-0.11Ω-34A- Max247 PowerMESHTM MOSFET(N溝道MOSFET) |
| STZTA92 | Medium Power Amplifier(硅平面外延工藝PNP晶體管) |
| SU-A36CH99-FREQ | PECL/LVPECL HF VCXO |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| STW81100ATR-1 | 功能描述:鎖相環(huán) - PLL MULTI BAND RF FREQ SYNTHESIZER RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| STW81101 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Multi-band RF frequency synthesizer with integrated VCOs |
| STW81101_07 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Multi-band RF frequency synthesizer with integrated VCOs |
| STW81101AT | 功能描述:鎖相環(huán) - PLL INTER-N FREQUENCY SYNTHESIZER RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| STW81101ATR | 功能描述:鎖相環(huán) - PLL WIRELESS INFRASTR. RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。