參數(shù)資料
型號(hào)： STV9937
廠商： 意法半導(dǎo)體
英文描述： 120-MHz On-Screen Display for Monitors including PictureBooSTTM and 4 True Independent Window Displays
中文描述： 120 - MHz的屏幕的顯示器，其中包括PictureBooSTTM和4個(gè)真正的獨(dú)立的窗口顯示顯示
文件頁(yè)數(shù)： 37/49頁(yè)
文件大小： 441K
代理商： STV9937
37/49
STV9937
General OSD Programming
Fast Blanking Output Polarity (FBLK output)
The output polarity of the FBLK pin is selected by bit FBLKPOL. The default value is 0.
8.5
Reset
Power On Reset
The digital core and the PLL are asynchronously reset at Power On.
Soft Reset
A soft reset is enabled by the RST bit.
RST = 1: The digital core is reset. All control registers including PictureBooST
TM
but with the
exception of PLL registers, are reset at the same value as at power on reset.
It is not necessary to write RST = 0 to stop the reset. This bit is automatically cleared.
PLL Register Reset
The Pixel Clock Generator (VCO[1:0]) and Horizontal Resolution (HR[6:0]) bits are reset by the
RST_PLL bit.
RST_PLL
= 1: HR[6:0] and VCO[1:0] are reset to the same value as the power-on reset.
It is not necessary to write RST_PLL = 0 to stop the reset. This bit is automatically cleared.
Table 44: Fast Blanking Output Polarity Selection
FBLKPOL
Description
0
When OSD display, FBLK = 1
When active video, FBLK = 0
1
When OSD display, FBLK = 0
When active video, FBLK = 1
Table 45: FBLK Output Control
ENOSD
Bit
FBLKPOL
Bit
FBK Bit
FBLK Output
Display
1
0
0
0
Video
Default Value
1
0
0
1
OSD
1
0
1
1
OSD
Full Screen
1
1
0
0
OSD
FBLK Inverted
1
1
0
1
Video
1
1
1
0
OSD
Full Screen
0
0
x
0
Video
No OSD
0
1
x
1
Video
No OSD
Table 46: Reset
FWR
FAC
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
80h
06h
RST_PLL
RST
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STV9937P 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:120-MHz On-Screen Display for Monitors including PictureBooSTTM and 4 True Independent Window Displays
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