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參數資料
| 型號： | STV9937 |
| 廠商： | 意法半導體 |
| 英文描述： | 120-MHz On-Screen Display for Monitors including PictureBooSTTM and 4 True Independent Window Displays |
| 中文描述： | 120 - MHz的屏幕的顯示器，其中包括PictureBooSTTM和4個真正的獨立的窗口顯示顯示 |
| 文件頁數： | 14/49頁 |
| 文件大?。?/td> | 441K |
| 代理商： | STV9937 |
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Window Specifications
STV9937
14/49
3.1
Enable Display
The Enable Display command for each window is selected by bits ENW1, ENW2, ENW3 and
ENW4. If the ENWi bit is set to 1, the corresponding window is displayed.
3.2
Origin Positions for the 4 Windows
The 4 windows are arranged in a frame whose origin coordinates are the horizontal delay (HD) and
the vertical delay (VD) located at the upper left-hand corner of the monitor screen. When the HD
and VD values are changed, the 4 windows within the frame position are automatically shifted by
the same value. The origin (HD, VD) can be programmed anywhere on the screen. Adjusting the
origin position is used to globally reposition the OSD windows.
The advantages of this system are easier programming, the possibility to adapt the position of all
windows at a single time without changing the relative position of each window and the possibility
for the user to program all 4 window positions.
3.2.1
General Horizontal Delay (HD)
The general horizontal delay defines the horizontal position of the origin coordinate for all four OSD
windows. The horizontal delay is selected by bits HD[6:0].
General Horizontal Offset = 50 pixels
General Horizontal Delay = HD[6:0] x 6 pixels + General Offset (in pixels)
The default value of the horizontal delay is 0h (left-hand side of the monitor screen).
3.2.2
General Vertical Delay (VD)
The general vertical delay defines the vertical position of the origin coordinate for all four OSD
windows. The vertical delay is selected by bits VD[7:0]. A general vertical offset of 2 scan lines is
also applied.
The range of the vertical delay is from 2 to 1022 scan lines, in steps of 4 scan lines each.
General Vertical Delay = VD[7:0] x 4 + 2 (in scan lines)
The default value of the vertical delay is 0h (top of screen).
Table 5: Enable Display
FWR
FAC
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
80h
07h
0h
ENW4
ENW3
ENW2
ENW1
Table 6: Origin of Windows on Horizontal Axis: Horizontal Delay
FWR
FAC
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
80h
04h
0h
HD[6:0]
Table 7: Origin of Windows on Vertical Axis: Vertical Delay
FWR
FAC
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
80h
05h
0h
VD[7:0]
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