參數(shù)資料
型號: STPCI2GDY
廠商: 意法半導體
英文描述: X86 Core PC Compatible System-on-Chip for Terminals
中文描述: x86內核PC兼容系統(tǒng)上的終端芯片
文件頁數(shù): 94/111頁
文件大?。?/td> 1896K
代理商: STPCI2GDY
DESIGN GUIDELINES
94/111
Issue 1.0 - July 24, 2002
memory clock input (MCLKI) and any other
component
using
the
individually driven from a low skew clock driver
with matched routing lengths. In other words, all
memory
clock
are
clock line lengths that go from the buffer to the
memory chips (MCLKx) and from the buffer to the
STPC (MCLKI) must be identical.
This is shown in
Figure 6-23
.
Figure 6-22. DIMM placement
DIMM2
DIMM1
STPC
35mm
35mm
15mm
10mm
116mm
SDRAM I/F
Figure 6-23. Clock Routing
MCLKO
DIMM CKn input
STPC MCLKI
DIMM CKn input
DIMM CKn input
Low skew clock driver:
L
L+75mm*
20pF
* No additional 75mm when SDRAM directly soldered on board
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